참고문헌
- Y. Zorian, 'A distributed BIST control scheme for complex VLSI devices,' Proc. of IEEE VLSI Test Symp., 1993, pp4-9 https://doi.org/10.1109/VTEST.1993.313316
- R.M. Chou, K. K. Saluja, and V.D. Agrawal, 'Scheduling test for VLSI systems under power constraints,' IEEE Trans. VLSI Syst., vol 5, pp.175-l85, June 1997 https://doi.org/10.1109/92.585217
- S.Wang and S.K. Gupta, 'LT-RTPG: A new test-per-scan BIST TPG for low heat disspation,' Proc. of Int. Test. Conf., 1990, pp. 84-94 https://doi.org/10.1109/TEST.1999.805617
- S.Gerstendorfer and H.J. Wunderlich, 'Minimized power consumption for scan-based BIST,' Proc. of Int. Test. Conf., 1999, pp.77-84 https://doi.org/10.1109/TEST.1999.805616
- P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitchm 'A test vector inhibiting technique for low energy BIST design,' Proc. of IEEE VLSI Test Symp., 1999, pp.407-412 https://doi.org/10.1109/VTEST.1999.766696
- F.Corno, M. Rebaudengo, and M. S. Reorda, 'Low power BIST via nonliear hybrid cellular automata,' Proc. of IEEE VLSI Test Symp., 2000. pp29-34 https://doi.org/10.1109/VTEST.2000.843823
- S. Wang and S. K. Gupta, 'ATPG for heat dissipation minimization during scan testing,' Proc. of Design Automation Conf., 1997, pp. 614-619 https://doi.org/10.1109/DAC.1997.597219
- R. Sankaralingam, R.R. Oruganti, and N.A Touba, 'Static compaction techniques to control scan vector power dissipation,' Proc. of IEEE VLSI Test Symp., 2000, pp. 35-40 https://doi.org/10.1109/VTEST.2000.843824
- K. Chakrabarty, 'Optimal test access architecture for system-on-chip,' ACM Trans. Design Automation Electron. Syst., vol. 6, pp. 26-49, Jan. 2001 https://doi.org/10.1145/371254.371258
- K. Chakrabarty, 'Design of system-on-chip test architectures under place-and-route and power constraints,' Proc. of IEEE/ ACM Design Automation Conf., 2000, pp.432-437 https://doi.org/10.1145/337292.337531
- Iyengar, V., Chakrabarty, K., Murray, B.T. 'Built-in self testing of seq. circuits using precomputed test sets,' Proc. of VLSI Test Symposium, 1998. pp.418-423 https://doi.org/10.1109/VTEST.1998.670900
- Hamzaoglu, I., Patel, J.H. 'Deterministic test pattern generation techniques for sequential circuits,' Computer Aided Design, 2000. ICCAD-2000. pp.538-543 https://doi.org/10.1109/ICCAD.2000.896528
- A. Jas, J. Ghosh-Dastidar, and N. A. Touba, 'Scan Vector Compression/Decompression Using Statistical Coding,' In Proceedings IEEE VLSI Test Symposium, pp. 114 - 121, 1999 https://doi.org/10.1109/VTEST.1999.766654
- A. Jas and N. Touba, 'Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core Based Designs,' In Proceedings IEEE International Test Conference, pp. 458 - 464, 1998 https://doi.org/10.1109/TEST.1998.743186
- A. Chandra and K Chakrabarty, 'System-on-a-Oiip Test Data Compression and Decompression Architectures Based on Golomb Codes,' IEEE Transactions on Computer Aided Design, Vol. 20, pp. 113 - 120, 2001 https://doi.org/10.1109/43.913754
- A. Chandra and K Chakrabarty, 'Frequency-Directed Run-Length (FDR) Codes with Application to System on a Chip Test Data Compression,' In Proceedings IEEE VLSI Test Symposium, pp. 114 - 121, 2001 https://doi.org/10.1109/VTS.2001.923416
- Girard, P., 'Survey of Low-power testing of VLSI Circuits,' Design & Test of Computers, IEEE Transactions on, Vol. 19 Issue. 3, 2002, pp.80-90 https://doi.org/10.1109/MDT.2002.1003802
- Klaus Holtz and Eric Holtz, 'Lossless Data Compression Techniques,' Proc. of Idea/ Microelectronics, 1994, pp.392-397
- B. Pouya and A. Crouch, 'Optimization Trade-offs for Vector Volume and Test Power,' Proc. of Int'l Test Conf.(IYC 00), IEEE Press, Piscata-way, N.J., 2000, pp.873-881 https://doi.org/10.1109/TEST.2000.894298
- Wolff F.G., Papachristou C., 'Multiscan-based test compression and hardware decompression using LZ77,' Proc. of Int. Test Conference, 2002. pp.331-339 https://doi.org/10.1109/TEST.2002.1041776
- P. Y. Gonciari, B. M AI-Hashimi, and N. Nicolici, 'Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression,' In Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp. 604 - 611, 2002 https://doi.org/10.1109/DATE.2002.998363
- Chandra, A., Chakrabarty, K, 'Low-power scan testing and test data compression for system-on-a-chip,' Computer-Aided Design of Integrated Circuits and Systema, IEEE Transactions on, Volume: 21, Issue: 5, May 2002 pp.597-604 https://doi.org/10.1109/43.998630