대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
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고속 디지털 신호처리를 위한 MBA기반 병렬 MAC의 효율적인 구조

A Efficient Architecture of MBA-based Parallel MAC for High-Speed Digital Signal Processing

  • 서영호 (광운대학교 Digital Design ＆ Test Lab.) ;
  • 김동욱 (광운대학교 Digital Design ＆ Test Lab.)
  • 발행 : 2004.07.01
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 고속의 곱셈-누적 연산을 수행할 수 있는 새로운 MAC(Multiplier- Accumulator)의 구조를 제안하였다. 부분 곱의 생성을 위해서 1의 보수 기반의 고속 Booth 알고리즘(Modified Booth Algorithm, MBA)를 이용하였고 다수의 부분 곱을 더하기 위해서 CSA(Carry Save Adder)를 이용하였다. 부분 곱을 더하는 과정에서 Booth 인코딩 시 이용한 1의 보수 체계를 2의 보수 체계로 보상하고 이전 합과 캐리를 누적하는 연산을 수행하여 고속의 누적 연산이 가능한 구조를 제안한다. 또한 부분 곱의 덧셈에서 하위 비트들을 2 비트 CLA(Carry Look-ahead Adder)를 이용하여 연산함으로써 최종 덧셈기의 입력 비트수를 줄임으로써 전체적인 임계경로를 감소시켰다. 제안된 MAC을 JPEG2000을 위한 DWT (Discrete Wavelet Transform) 필터링 연산에 적용하여 고속의 디지털 신호처리가 가능함을 보였고 기존의 연구와 비교하여 향상된 성능을 보이는 것을 확인하였다.

In this paper, we proposed a new architecture of MAC(Multiplier-Accumulator) to operate high-speed multiplication-accumulation. We used the MBA(Modified radix-4 Booth Algorithm) which is based on the 1's complement number system, and CSA(Carry Save Adder) for addition of the partial products. During the addition of the partial product, the signed numbers with the 1's complement type after Booth encoding are converted in the 2's complement signed number in the CSA tree. Since 2-bit CLA(Carry Look-ahead Adder) was used in adding the lower bits of the partial product, the input bit width of the final adder and whole delay of the critical path were reduced. The proposed MAC was applied into the DWT(Discrete Wavelet Transform) filtering operation for JPEG2000, and it showed the possibility for the practical application. Finally we identified the improved performance according to the comparison with the previous architecture in the aspect of hardware resource and delay.

키워드

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