Journal of the Institute of Electronics Engineers of Korea TC (대한전자공학회논문지TC)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지

An Efficient Central Queue Management Algorithm for High-speed Parallel Packet Filtering

고속 병렬 패킷 여과를 위한 효율적인 단일버퍼 관리 방안

  • 임강빈 (순천향대학교 정보보호학과) ;
  • 박준구 (디지털스트림테크놀로) ;
  • 최경희 (아주대학교 정보 및 컴퓨터공학) ;
  • 정기현 (아주대학교 전자공학부)
  • Published : 2004.07.01
Download PDF
⟨ Previous Next ⟩

Abstract

This paper proposes an efficient centralized sin91e buffer management algorithm to arbitrate access contention mon processors on the multi-processor system for high-speed Packet filtering and proves that the algorithm provides reasonable performance by implementing it and applying it to a real multi-processor system. The multi-processor system for parallel packet filtering is modeled based on a network processor to distribute the packet filtering rules throughout the processors to speed up the filtering. In this paper we changed the number of processors and the processing time of the filtering rules as variables and measured the packet transfer rates to investigate the performance of the proposed algorithm.

본 논문은 고속의 병렬 패킷 여과를 위한 다중프로세서 시스템이 가지는 단일 버퍼에서 단일 버퍼의 판독을 위한 다중프로세서 간의 경합을 중재하기 위한 효율적인 단일 버퍼 관리 방안을 제안하고 이를 실제의 다중 프로세서 시스템에 적용하여 실험함으로써 제안한 방안이 납득할 만한 성능을 제공함을 증명하였다. 병렬 패킷 여과시스템으로는 처리의 고속화를 위하여 패킷 여과규칙을 다중의 프로세서에 걸쳐 분산 처리하는 경우를 모델로 정하였다. 실제의 실험은 다중 프로세서를 가지는 네트워크 프로세서에서 이루어졌으며 100Mbps 의 통신망을 배경으로 하였다. 제안한 방안의 성능을 고찰하기 위하여 프로세서 수의 변화 및 여과 규칙의 처리 시간의 변화 등에 따르는 실제 패킷 전송률을 측정하였다.

Keywords

References

  1. Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad, Characterizing Processor Architectures for Programmable Network Interfaces, International Conference on Supercomputing https://doi.org/10.1145/335231.335237
  2. Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, On the Performance of Multithreaded Architectures for Network Processors, 2001
  3. Tammo Spalink, Scott Karlin, Larry Peterson, Evaluating Network Processors in IP Forwarding, Department of Computer Science, Prinston University, Technical Report, 2000
  4. Prashanth Pappu, Tilman Wolf, Scheduling Processing Resources in Programmable Routers, Washinton University in St. Louis, 2001
  5. T. Spalink, S. Karlin, L. Peterson, and Y. Gottlieb, Building a robust software-based router using network processors, In Proc. Symposium on Operating Systems Principles (2001) https://doi.org/10.1145/502034.502056
  6. Scott Karlin and Larry Peterson, Maximum Packet Rates for Full-Duplex Ethernet, Technical Report TR-645-02, February 14, 2002
  7. Norman C. Huntchinson and Larry L. Peterson, The x-kernel: An architecture for implementing network protocols, IEEE Transactions on Software Engineering, 17(1):64-76, January 1991 https://doi.org/10.1109/32.67579
  8. James D. Salei, Scheduling Parallel Networking on Shared-Memory Multiprocessors, A ph.D.Dissertation Proposal at Department of Computer Science, University of Massachusetts
  9. Takeshi Miei. Mitsuru Maruyama, Tsuyushi Ogura, Naohisa Takahashi, Parallelization of IP-Packet Filter Rules, IEEE 1997
  10. Intel IXP1200 Network Processor Family, Davelopment Tools user's Guide, Intel, December, 2001
  11. DPF: Fast, Flexible Message Demultiplexing using Dynamic Code Generation
  12. Venkatachary Srinivasan and George Varghese, Faster IP Lookups using Controlled Prefix Expansion, Measurement and Modeling of Computer Systems
  13. Intel IXP1200 Network Processor Family, Hardware Reference Manual, Intel Corp. December, 2001
  14. Qiwei Huang, Errol Lloyd, Analysis of Queuing Delay in Multimedia Gateway Call Routing, CS REA, IC 2002
  15. Carsten Benecke, A Parallel Packet Screen for High Speed Networks, Proceedings of the 15th Annual Computer Security Applications Conference 1999 https://doi.org/10.1109/CSAC.1999.816014
  16. J. Wu and M. Singhal. Design of A High-Performance ATM Firewall. In Proceeding: 5th ACM Conference on Computer and Communications Security, San Francisco, California, November 4-5 1998 https://doi.org/10.1145/288090.288113
  17. Thomas Y. C. Woo, A Modular Approach to Packet Classification: Algorithms and Results, INFOCOM, p1213-1222, 2000 https://doi.org/10.1109/INFCOM.2000.832499