The Transactions of the Korean Institute of Electrical Engineers C (대한전기학회논문지:전기물성ㆍ응용부문C)

The Korean Institute of Electrical Engineers (대한전기학회)
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An Analytic Study on Estimating Delay Time in RC-class Interconnects Under Saturated Ramp Inputs

램프 입력에 대한 RC-class 연결선의 지연시간 예측을 위한 해석적 연구

  • Published : 2004.04.01
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Abstract

This paper presents a simple and fast delay metric RC-class interconnects under saturated ramp inputs. The RC delay metric under saturated ramp inputs, called FDM(Fast Delay Metric), can estimate delay times at an arbitrary node using a simple closed-form expression and is extended from delay metric under step input easily As compared with similar techniques proposed in previous researches, it is shown that the FDM technique complexity for a similar accuracy. As the number of circuit nodes increases, there will be a significant difference in estimation times of RC delay between the previous techniques based on two circuit moments and the FDM which do not depend on circuit moments.

Keywords

References

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