고속 QPSK/16-QAM 수신기 칩 설계

Design of a High Speed QPSK/16-QAM Receiver Chip

  • 발행 : 2003.04.01

초록

본 논문에서는 QPSK/16-QAM 방식의 LMDS(Local Multipoint Distribution Services) 용 downstream 수신기 칩 설계에 대해서 기술한다. 제안된 칩은 블라인드 등화기, 심볼 타이밍 복구회로, 반송파 복구회로로 구성된다. 블라인드 등화기는 CMA(Constant Module Algorithm)를 이용한 DFE(Decision Feedback Equalizer) 구조로 사용했다. 심볼 타이밍 복구회로는 Parabolic Interpolator를 이용하였고 반송파 복구회로는 Decision Directed Basis 방식을 이용하여 반송파의 주파수 옵셋, 위상 옵셋, 위상지터(Jitter)를 제거하였다. 구현된 수신기는 10, 20, 30 그리고 40 Mbps 의 4가지 데이터 전송률을 지원할 수 있고 심볼 전송률은 10 Mbaud까지 지원할 수 있으며 기존의QAM 수신기보다 빠른 구조이다.

This paper presents the design of a QPSK/16-QAM downstreams receiver chip. The proposed chip consists of a blind equalizer, a timing recovery block and a carrier recovery block. The blind equalizer uses a DFE sturucture using CMA(Constant Module Algorithm). The symbol timing recovery uses the modified parabolic interpolator. The decision-directed carrier recovery is used to remove the carrier frequency offset, phase offset and phase jitter. The implemented LMDS receiver can support four data rates, 10, 20, 30 and 40 Mbps and can accommodate the symbol rate up to 10 Mbaud. This symbol rate is faster than existing QAM receivers.

키워드

참고문헌

  1. DAVIC, DAVIC 1.4 Specification Part 8 Lower Layer Protocols and Physical Interfaces, 1998
  2. 주성철, '대화형 CATV 시스템 개발 현황,' 전자공학회지, 제 22권, 제 7호, pp.60-70
  3. BROADCOM, QAMLink Universal Burst Receiuer, 1997
  4. D. D. Falconer, 'Jointly adaptive equalization and carrier recovery in two dimensional digital communication systems,' Bell Syst. Tech J., vol. 55, pp. 317-334, May 1976 https://doi.org/10.1002/j.1538-7305.1976.tb03317.x
  5. F. R. P. Cavalcanti and J. C. M. Mota, 'A predictive constant modulus algorithm for blind equalization in QAM systems,' in Proc. IEEE Int. Conf. Commun., vol. 2/3, 1997. pp. 1080-1084
  6. L. K. Tan, J. S. Putnam. F. Lu, L. J. D'Luna, D. W. Mueller, K. R. Kindsfater, K. B. Cameron, R. B. Joshi, R. A. Hawley, and H. Samueli, 'A 70-Mb/s variablerate 1024-QAM cable receiver IC with integrated lO-b ADC and FEC decoder' IEEE J. Solid-State Circuits, vol. 33, pp. 2205-2218, Dec. 1998 https://doi.org/10.1109/4.735705
  7. M. T. Shiue, C. K. Wang, and W. I. Way, 'A VLSI architecture design for dual mode QAM and VSB digital CATV transceiver,' IEICE Trans. Commun., vol. E81 B, pp. 2351-2356, Dec. 1998
  8. R. B. Joshi, B. Daneshrad, and H. Samueli, 'A VLSI architecture for a single-chip 5-Mbaud QAM receiver,' in Proc. IEEE Globecom, 1992, pp. 1265-1268
  9. K. Yamanaca, S. Takeuchi, S. Murakami, M. Koyama, J. Ido, T. Fujiwara, S. Hirano, K. Okada, and T. Sumi, 'A multilevel QAM demodulator VLSI with wideband cairier recovery and dual equalizing mode,' IEEE J. Solid-State Circuits, vol. 32, pp. 1101-1107, July. 1997 https://doi.org/10.1109/4.597300
  10. L. Erup, F. M. Gardner, and R. A. Harris, 'Interpolation in digital modems-partn: implementation and performance,' IEEE Trans. Commun., vol. 41, pp. 998-1008, June 1993 https://doi.org/10.1109/26.231921
  11. F. M. Gardner, 'A BPSK/QPSK timing-error detector for sampled receivers,' IEEE Trans. Commun., vol. C0MU 34, pp. 423-429, May 1986 https://doi.org/10.1109/TCOM.1986.1096561
  12. R. L. Cupo, and R. D. Gitlin, 'Adaptive carrier recovery system for digital data communications receivers' IEEE J. Select. Areas Commun., vol. 7, pp. 1328-1339, Dec. 1989 https://doi.org/10.1109/49.44576
  13. 최 형진, 동기방식 디지털 통신, 교학사, 1995