논리결함 검사를 위한 Pattern Generator의 PLD 회로 설계

The PLD Circuit Design of Pattern Generator for the Logical Inspection of Logical Defection

In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.