JSTS:Journal of Semiconductor Technology and Science

  • 제3권4호
  • /
  • Pages.167-174
  • /
  • 2003
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  • 1598-1657(pISSN)
  • /
  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Design and Implementation of Content Switching Network Processor and Scalable Switch Fabric

  • Chang, You-Sung (Korea Advanced Institute of Science and Technology(KAIST), Paion Co., Ltd.) ;
  • Yi, Ju-Hwan (Korea Advanced Institute of Science and Technology(KAIST)) ;
  • Oh, Hun-Seung (Korea Advanced Institute of Science and Technology(KAIST)) ;
  • Lee, Seung-Wang (Korea Advanced Institute of Science and Technology(KAIST)) ;
  • Kang, Moo-Kyung (Korea Advanced Institute of Science and Technology(KAIST)) ;
  • Chun, Jung-Bum (Korea Advanced Institute of Science and Technology(KAIST)) ;
  • Lee, Jun-Hee (Korea Advanced Institute of Science and Technology(KAIST)) ;
  • Kim, Jin-Seok (Korea Advanced Institute of Science and Technology(KAIST)) ;
  • Kim, Sang-Ho (Korea Advanced Institute of Science and Technology(KAIST)) ;
  • Jung, Hee-Jae (Korea Advanced Institute of Science and Technology(KAIST)) ;
  • Hong, Il-Sung (Seoul National University) ;
  • Kim, Yong-Hwan (LG semiconductor) ;
  • Lee, Yu-Sik (LG semiconductor, Hynix, and Vision Telecom) ;
  • Kyung, Chong-Min (Department of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST))
  • 발행 : 2003.12.01
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초록

This paper proposes a network processor especially optimized for content switching. With 2Gbps port capability, it integrates packet processor cluster, content-based classification engine and traffic manager on a single chip. A switch fabric architecture is also designed for scale-up of the network processor's capability over hundreds gigabit bandwidth. Applied in real network systems, the network processor shows wire-speed network address translator (NAT) and content-based switching performance.

키워드

참고문헌

  1. H. S. Oh, Y. S. Chang, C. M. Kyung, 'An Area-Efficient Architecture for Content-Based, Real-Time Packet Classification', submitted to IEEE Tr. on VLSI
  2. Iyer, S., Kompella, R., and Shelat, A.: 'ClassiPI: An architecture of fast and flexible packet classification'. IEEE Network, vol. 15, pp. 33-41, Mar./Apr. 2001 https://doi.org/10.1109/65.912718
  3. F. M. Chiussi and A. Francini, 'Scalable electronic packet switches', Selected Areas in Communications, IEEE Journal on, Vo1 21, Issue 4, May 2003 https://doi.org/10.1109/JSAC.2003.810497
  4. GEP2C02 Network Processor Datasheet, June, 2003
  5. GES0016 Switch Fabric Datasheet, June, 2003