Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Buffered Routing Tree Construction under Buffer Location and Wiring Constraints

버퍼 삽입 위치 및 배선 제한을 고려한 Buffered 배선 트리 구성

  • Published : 2003.11.01
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Abstract

In this paper, a simultaneous buffer insertion and routing method is proposed under the constraints of wire and buffer locations by macro or IP blocks. A new grid graph is proposed to describe the regions in which buffers(or both wires and buffers) are not available. Under this grid we describe a method of constructing a buffeted tree that minimize the maximum source to sink delay. The method is based on the dynamic programming with pruning unnecessary partial solutions. The proposed method improved the slack time of the delay by 19% on the average while using less buffers and similar wire length.

본 논문에서는 매크로 또는 IP 블록 같은 장애물로 인하여 버퍼삽입과 배선에 제한이 있는 환경에서 연결 지연시간을 최소화하기 위한 배선 및 버퍼삽입위치를 동시에 구하는 방법을 제안한다. 제안한 방법에서는 새로운 격자그래프를 도입하여 배선 또는 버퍼삽입이 불가능한 영역을 효과적으로 표현하고 이 격자그래프 상에서 동적 프로그래밍을 사용하여 배선 트리의 구성과 동시에 버퍼의 삽입여부 및 위치를 구한다. 제안한 방법은 기존 방법에 비하여 유사한 배선길이 및 작은 수의 버퍼를 삽입하면서도 평균 19% 정도의 여유 지연시간이 향상되었다.

Keywords

References

  1. C.J. Alpert and A. Devgan, 'Wire Segmenting for Improved Buffer Insertion,' Proc. of DAC, 1997, pp. 588-593
  2. C.J. Alpert, et al., 'Steiner Tree Optimization for Buffers, Blockages, and Bays,' IEEE TCAD, Vol. 20, No. 4, pp. 556-562, Apr. 2001 https://doi.org/10.1109/43.918213
  3. C.J. Alpert, et al., 'Buffered Steiner Trees for Difficult Instances,' Proc. of ISPD, 2001, pp. 4-9 https://doi.org/10.1145/369691.369699
  4. C.J. Alpert, et al., 'A Practical Metho- dology for Early Buffer and Wire Resource Allocation,' Proc. of DAC, 2001, pp. 189-194
  5. J. Cong, et al., 'Efficient Algorithms for the Minimum Shortest Path Steiner Arbore- scence Problem with Applications to VLSI Physical Design,' IEEE TCAD, Vol. 17, No. 1, pp. 24-39, January 1998
  6. J. Cong and X. Yuan, 'Routing Tree Construction Under Fixed Buffer Location,' Proc. of DAC, 2000, pp. 379-384 https://doi.org/10.1145/337292.337502
  7. W.C. Elmore, 'The Transient Response of Damped Linear Network with Particular Regard to Wideband Amplifier,' J. Applied Physics, pp. 55-63, 1948 https://doi.org/10.1063/1.1697872
  8. L. P.P.P. van Ginneken, 'Buffer Placement in Distributed RC-tree Networks for Minimal Elmtore Delay,' Proc. ISCAS, 1990, pp. 865-868 https://doi.org/10.1109/ISCAS.1990.112223
  9. J. Hu et al., 'Buffer Insertion with Adap- tive Blockage Avoidance,' Proc. ISPD, 2002, pp. 92-97 https://doi.org/10.1145/505388.505412
  10. T. Okamoto and J. Cong, 'Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization,' Proc. of ICCAD, 1996, pp. 44-49 https://doi.org/10.1109/ICCAD.1996.568938
  11. H. Zhou et al., 'Simultaneous Routing and Buffer Insertion with Restricts on Buffer Locations,' IEEE TCAD, Vol. 19, No. 7, pp. 819-824, July 2000 https://doi.org/10.1109/43.851998