다수 입력용 전류모드 Max 회로에서 다이오드결선 트랜지스터의 트랜스컨덕턴스 조정에 의한 고주파 왜곡 억제

Suppression of the High Frequency Distortion by Adjustment of Transconductance of the Diode-Connected Transistor in the Current Mode Max Circuit for Multiple Inputs

  • 이준수 (전북대학교 제어계측공학과) ;
  • 손홍락 (전북대학교 제어계측공학과) ;
  • 김형석 (전북대학교 제어계측공학과)
  • 발행 : 2003.11.01

초록

다수의 입력을 필요로 하는 전류모드 Max 회로에서 고주파 왜곡을 효과적으로 억제할 수 있는 trans conductance 조정 방법을 제안하였다. Max 회로에 인가되는 입력 신호의 개수가 증가하면, 기생 커패시턴스는 입력 단의 개수에 비례하여 누적되게 된다. 본 연구에서는 Max 회로의 왜곡 신호의 크기가 누적된 기생 커패시턴스와 출력신호의 변화율에 비례하며, 공통 다이오드결선 트랜지스터의 transconductance 값에 반비례하게 됨을 밝혔다. 왜곡 억제를 위한 효과적인 방안으로 공통 다이오드결선 트랜지스터의 transconductance 값을 최소화하는 방안을 제시하였다. 이 방법의 효용성은 다양한 수의 입력 신호를 갖는 전류모드 Max 회로에 대해서 HSPICE 시뮬레이션을 통해 입증하였다.

A distortion suppression technology for employing multiple inputs in 3n+1 type current mode Max circuit is proposed using the adjustment of transconductance. If the number of input blocks of the current mode Max circuit increases, the high frequency distortion in the output signal grows. In this paper, it has been disclosed that the distortion in the multiple input Max circuit is proportional to such accumulated parasitic capacitance, to the derivative of the output signal and also to tile inverse of transconductance of the common diode-connected transistor. The proposed idea is by employing as larger transconductance of the common diode-connected transistor as possible. The effectiveness of the proposed idea has been proved through the HSPICE simulation for the current mode Max circuits with various numbers of input signals.

키워드

참고문헌

  1. Z.S. Gunay and E. Sanchez-Sinencio, 'CMOS winner-take-all circuits : a detail comparison,' IEEE International Symposium on Circuits and Systems. vol. 1, pp. 41-44, June 1997 https://doi.org/10.1109/ISCAS.1997.608514
  2. R.G. Carvajal, J. Ramirez-Angulo, and J. Tomba, 'High-speed high-precision voltage-mode MIN/MAX circuits in CMOS technology,' IEEE International Symposium on Circuits and Systems, pp. 13-16, May 2000 https://doi.org/10.1109/ISCAS.2000.857351
  3. J. Lazzaro, S. Ryckebusch, M.A. Mahowald, and C.A. Mead, 'Winner-take-all networks of O(n) complexity,' Advances in Neural Signal Processing Systems, vol. 1, pp. 703-711, 1989
  4. D.M. Wilson, and S.P. Deweerth, 'Winning Isn't Everything,' ISCAS'95, pp. 105-108, May 1995
  5. R. Kalim, and D.M. Wilson, 'Semi-parallel rank-order filtering in analog VLSI,' ISCAS'99, pp. 232-235, May 1999 https://doi.org/10.1109/ISCAS.1999.780676
  6. T. Yamakawa and T. Miki, 'The current-mode fuzzy logic integrated circuits fabricated by the standard CMOS process,' IEEE Trans. On Computers, vol. C-35, (2), pp. 161-167, February, 1986 https://doi.org/10.1109/TC.1986.1676734
  7. M. Sasaki, T. Inoue, Y. Shirai and F. Ueno, 'Fuzzy multiple-input maximum and minimum circuits in current mode and their analyses using bounded-difference equations,' IEEE Trans. On Computers. vol. C-39, (6), pp. 768-774, June 1990 https://doi.org/10.1109/12.53598
  8. I. Baturone, J.L. Huertas, A. Barriga, and S. Sanchez-Solano, 'Current-mode multiple-input maximum circuit,' Electron. Lett., vol. 30, (9), pp. 678-680, April 1994 https://doi.org/10.1049/el:19940510
  9. I. Baturone, A. Barriga, and J.L. Huertas, 'Multi-input voltage and current-mode min/max circuits,' Proc. 3rd Int. Conf. on Fuzzy Logic, Neural Networks and Soft Computing, pp. 120-126, 1994
  10. C.Y. Huang and B.D. Liu, 'Current-mode multiple input maximum circuit for fuzzy logic controllers,' Electronics Letters, vol. 30, (23), pp. 1924-1925, November 1994 https://doi.org/10.1049/el:19941342