Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low System Complexity Bit-Parallel Architecture for Computing $AB^2+C$ in a Class of Finite Fields $GF(2^m)$

시스템 복잡도를 개선한 $GF(2^m)$ 상의 병렬 $AB^2+C$ 연산기 설계

  • 변기령 (가톨릭대학교 정보통신전자공학부) ;
  • 김흥수 (인하대학교 전자공학과)
  • Published : 2003.11.01
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Abstract

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.

본 논문에서는 m차 기약 AOP를 적용하여 시스템 복잡도를 개선한 GF(2/sup m/)상의 새로운 AB²＋C 연산기법과 그 하드웨어 구현회로를 제안하였다. 제안된 회로는 병렬 입출력 구조를 가지며, CS, PP 및 MS를 모듈로 하여 구성되며 이들은 각각 AND와 XOR 게이트의 규칙적인 배열구조를 갖는다. 제안된 회로의 시스템 복잡도는 (m＋1)²개의 2-입력 AND게이트와 (m＋1)(m＋2)개의 2-입력 XOR게이트의 회로복잡도와 연산에 소요되는 최대 지연시간은 T/sub A/sup ＋/(1＋「log₂/sup m/」)T/sub x/ 이다. 제안된 연산기의 시스템 복잡도와 구성상의 특징을 타 연산기를 표로 비교하였고, 그 결과 상대적으로 우수함을 보였다. 또한, 단순하면서도 정규화된 소자 및 결선의 구조는 VLSI 구현에 적합하다.

Keywords

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