The Transactions of the Korean Institute of Electrical Engineers D (대한전기학회논문지:시스템및제어부문D)

The Korean Institute of Electrical Engineers (대한전기학회)
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Design of R=1/2, K=7 Type High Speed Viterbi Decoder with Circularly Connected 2-D Analog Parallel Processing Cell Array

아날로그 2차원 셀의 순환형 배열을 이용한 R=l/2. K=7형 고속 비터비 디코더 설계

  • 손홍락 (전북대 공대 전자공학과) ;
  • 김형석 (전북대 공대 전자정보공학부)
  • Published : 2003.11.01
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Abstract

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing ceil array Is proposed. The proposed Viterbi .decoder has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram, the output column of the analog processing cells is connected to the decoding column, and thus, the output(last) column becomes a column right before the decoding(first) column. The reference input signal given at a decoding column is propagated to the whole network while Its magnitude is reduced by the amount of a error metric on each branch. The circuit-based decoding is done by adding a trigger signals of same magnitudes to disconnect the path corresponding to logic 0 (or 1) and by observing its effect at an output column (the former column of the decoding column). The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

Keywords

References

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