대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Evanescent-Mode를 이용한 MOSFET의 단채널 효과 분석

Evanescent-Mode Analysis of Short-Channel Effects in MOSFETs

  • 이지영 (이화여자대학교 정보통신학과) ;
  • 신형순 (이화여자대학교 정보통신학과)
  • 발행 : 2003.10.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

Super-steep retrograded channel (SSR)을 갖는 bulk MOSFET, fully-depleted SOI, double-gate MOSFET 구조에 대하여 단채널 효과를 비교 분석하였다. Evanescent-mode를 이용하여, 각 소자 구조에 대한 characteristics scaling-length (λ)를 추출할 수 있는 수식을 유도하고 추출된 λ의 정확도를 소자 시뮬레이션 결과와 비교하여 검증하였다. 70 nm CMOS 기술에 사용 가능하도록 단채널 효과를 효과적으로 제어하기 위해서는 최소 게이트 길이가 5λ 이상이어야 하며 SSR 소자의 공핍층 두께는 약 30 nm 정도로 스케일링되어야 한다. High-κ 절연막은 equivalent SiO2 두께를 매우 작게 유지하지 않을 경우 절연막을 통한 드레인 전계의 침투 때문에 소자를 스케일링하는데 제한을 갖는다.

Short channel effects (SCE) of bulk MOSFET with super-steep retrograded channels (SSR), fully-depleted SOI, and double-gate MOSFET have been analyzed using a evanescent-mode analysis. Analytical equations of the characteristics scaling-length (λ) for three structures have been derived and the accuracy of the calculated λ was verified by comparing to the device simulation result. It is found that the minimum channel length should be larger than 5λ and the depletion thickness of the SSR should be around 30 nm in order to be applicable to 70 nm CMOS technology. High-$textsc{k}$ dielectric shows a limitation in scaling due to the drain-field penetration through the dielectric unless the equivalent SiO2 thickness is very thin.

키워드

참고문헌

  1. International Technology Roadmap for Semiconductors 2001 edition, http://public.itrs.net/files/2001ITRS/Home.htm
  2. I. De and C. M. Osburn, 'Impact of Super-Steep-Retrograde Channel Doping Profiles on the Performance of Scaled Devices,' IEEE Transactions on Electron Device, IEEE Transactions on Electron Device, ED-46, p. 1711, 1999 https://doi.org/10.1109/16.777161
  3. H. Meer and K. Meyer, 'The Spacer/Replacer Concept: A Viable for Sub-100 nm Ultrathin-Film Fully-depleted SOI CMOS', IEEE Electron Device Letters, EDL-23, p. 46, 2002 https://doi.org/10.1109/55.974808
  4. K. Kim and J. G. Fossum, 'Double-Gate CMOS: Symmetrical-Versus Asymmetrical-Gate Devices', IEEE Transactions on Electron Device, ED-48, p. 294, 2001 https://doi.org/10.1109/16.902730
  5. M. Ieong, H. Wong, E. Nowak, J. Kedziers, and E. Jones, 'High Performance Double-Gate Device Technology Challenges and Oppor-tunities', in Proceedings of International Symposium on Quality Electronic Design, p. 18, March 2002 https://doi.org/10.1109/ISQED.2002.996793
  6. MEDICI V.2001.4, Fremont: Avant!, 2001
  7. D.J. Frank, Y. Taur, and H. P. Wong, 'Generalized Scale Lengh for Two-Dimensional Effects in MOSFET's', IEEE Electron Device Letters, EDL-19, p. 385, 1989 https://doi.org/10.1109/55.720194
  8. S.H. Oh, D. Monroe, and J.M. Hergenrother, 'Analytic Description of Short-Channel Efects in Fully-Depleted Double-Gate and Cylindrical, Surrounding-Gate MOSFETs', IEEE Electron Device Letters, EDL-21, p. 445, 2001 https://doi.org/10.1109/55.863106
  9. T.N. Nguyen, 'Small-geometry MOS Transistors: Physics and Modeling of Surface-and Buried-Channel MOSFETs', Ph.D. dissertation, Stanford Univ., Stanford, CA, 1984
  10. S. Wolf, Silicon Processing for the VLSI Era, Vol. 3 - The submicron MOSFET, New York: Lattice Press, 1995, p.235
  11. Ph.D. dissertation, Stanford Univ. Small-geometry MOS Transistors:Physics and Modeling of Surface-and Buried-Channel MOSFETs T.N.Nguyen