The KIPS Transactions:PartA (정보처리학회논문지A)

Korea Information Processing Society (한국정보처리학회)
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The Design and Implementation of Verilog-2001 Parser

Verilog-2001 파서의 설계와 구현

  • 김영수 (한국전자통신연구원 시스템 IC 설계팀) ;
  • 김태석 (한국전자통신연구원 시스템 IC 설계팀) ;
  • 김상필 (한국전자통신연구원 시스템 IC 설계팀) ;
  • 조한진 (한국전자통신연구원 시스템 IC 설계팀)
  • Published : 2003.08.01
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Abstract

The Verilog parser libary for IEEE Verilog 1364-2001 Standard is developed in the paper. The lexer and scanner are developed and tested to handle "Yerilog-2001" which is the first major update to the Verilog language since its inception in 1984. Also the newly developed XML intermediate format for Verilog-2001 is presented. By using the XML intermediate, it allows the portable and scalable development of various kinds of verilog applications that are mainly focused on semantic manipulation.ipulation.

본 논문에서는 IEEE Verilog 1364-2001 표준을 지원하는 Verilog-2001 파서를 개발하였다. 개발된 파서의 어휘 분석 및 구문 분석기는 Verilog-2001을 지원할 수 있도록 개발되었으며 Verilog-2001 테스트 슈트(test suite)를 개발하여 검증하였다. XML 중간형식을 설계하여 사용함으로써 Verilog시맨틱 조작의 응용에 적합하게 설계되었으며 기존의 구조 수준의 파서의 단점을 극복하기 위하여 문맥 정보의 처리가 가능하도록 개발되었다.

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References

  1. S. Cheng, R. Brayton, G. York, K. Yelick and A. Saldanha, 'Compiling Verilog into timed finite state machines,' Verilog HDL Conference, pp.32-39, 1995
  2. C. Dawson, S. Pattanam and D. Roberts, 'The Verilog Procedural Interface for the Verilog Hardware Description Language,' Verilog HDL Conference, pp.17-23, 1996
  3. J. Dimitrov, 'Operational semantics for verilog,' Proceedings of Eighth Asia-Pacific Software Engineering Conference, pp.161-168, 2001
  4. B. Bailey and D. Gajski, 'RTL semantics and methodology,' Proceedings of the 14th International Symposium on System Syntheis, pp.69-74, 2001 https://doi.org/10.1145/500001.500017
  5. The IEEE Verilog 1364-2001 Standard What's New, and Why Need It, Stuart Sutherland, 9th Annual International Conference and Exhibition, March, 2000
  6. 1364-2991 IEEE Standard for Verilog Hardware Description Language, 2001
  7. IEEE Std. 1364.1-2002 IEEE Standard for Veilog Register Transfer Level Syntheis, 2002
  8. H. Eriksson and M. Penker, 'UML Toolkit,' John Wiley & Sons, Inc., 1998
  9. ANTLR web site, http://www.antlr.org/
  10. T. Parr, 'Language Translation Using PCCTS & C++,' Automata Publishing Company, 1997
  11. M. Reshadi, A. Gharehbaghi and Z. Navabi, 'AIRE/CE : a revision towards CAD tool integration,' Proceedings of the 12th International Conference on Microelectronics, pp.277-280, 2000
  12. T. Karayiannis, J. Mades, T. Schenider, A. Windisch, and W. Ecker, 'Using XML for representation and visualization of elaborated VHDL-AMS models,' VHDL International Users Forum Fall Workshop, pp.83-87, 2000 https://doi.org/10.1109/VIUF.2000.890273
  13. E. A. Lee and S. Neuendorffer, 'MoML A Modeling Mark-up Language in XML Version 0.4,' Technical Memorandum ERL/UCB M 00/12, 2000
  14. N. Kai and M. Luoming, 'Design and implementation of the DTD-based XML parser,' Proceedings of International Conference on Communication Technology, , pp.1634-1637, 2003 https://doi.org/10.1109/ICCT.2003.1209841
  15. J. Gi and C. Hirata, 'XACDML-extensible ACD markup language,' Proceedings of 36th Annual Simulation Symposium, pp.343-350, 2003
  16. L. Lan, L. Xi, X. Yue and Z. Xuehai, 'XM-ADL, an extensible markup architecture description language,' Proceedings of 15th Annual IEEE International ASIC/SOC Conference, pp.63-67, 2002
  17. EdaXML, http://www.e-tools.com/
  18. F. Boumphrey et al., 'Professional XML Applications,' WROX, 1999
  19. Icarus Verilog Test Suite, http://www.icarus.com/eda/verilog/
  20. Matthew H. Austern, Generic Programming and the STL : Using and Extending the C++ Standard Template Library, Addison-Wesley, Reading, MA, 1999
  21. Nicolai M. Josuttis, The C++ Standard Template Library : A Tutorial and Reference, Addison-Wesley, Boston, MA, 1999