대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

새로운 DCME 알고리즘을 사용한 고속 Reed-Solomon 복호기

High-Speed Reed-Solomon Decoder Using New Degree Computationless Modified Euclid´s Algorithm

  • 발행 : 2003.06.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 차수 연산이 필요 없는 새로운 DCME 알고리즘 (Degree Computationless Modified Euclid´s Algorithm)을 사용한 저비용 고속 RS (Reed-Solomon) 복호기를 제안한다. 제안하는 구조는 차수 연산 및 비교 회로가 필요 없어 기존 수정 유클리드 구조들에 비해 매우 낮은 하드웨어 복잡도를 갖는다. 시스톨릭 에레이 (systolic array)를 이용한 제안하는 구조는 키 방정식 (key equation) 연산을 위해서 초기 지연 없이 2t 클록 사이클만을 필요로 한다. 또한, 3t＋2개의 기본 셀 (basic cell)을 사용하는 DCME 구조는 오직 하나의 PE (processing element)를 사용하므로 규칙성 (regularity) 및 비례성(scalability)을 갖는다. 0.25㎛ Faraday 라이브러리를 사용하여 논리합성을 수행한 RS 복호기는 200㎒의 동작 주파수 및 1.6Gbps의 데이터 처리 속도를 갖는다. (255, 239, 8) RS 코드 복호를 수행하는 DCME 구조와 전체 RS 복호기의 게이트 수는 각각 21,760개와 42,213개이다. 제안하는 RS 복호기는 기존 RS 복호기들에 비해 23%의 게이트 수 절감 및 전체 지연 시간의 10%가 향상되었다.

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

키워드

참고문헌

  1. A. Raghupathy and K. J. R. Liu, 'Algorithm-based low-power/high-speed Reed-Solomon decoder design,' IEEE Trans. Circuit Syst. II, vol. 47, pp. 1254-1270, Nov. 2000 https://doi.org/10.1109/82.885132
  2. HomePlug Powerline Alliance, Medium Interface Specification Release 0.5, Nov. 2000
  3. DVB, Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television, ETSI EN 300 744 v1.41, Jan. 2001
  4. ATSC, ATSC Digital Television Standard, ATSC standard A/53B, Aug. 2001
  5. DAVIC 1.4 Specification Part 08, Lower Layer Protocols and Physical Interface, 1998
  6. A. M. Michelson and A. H. Levesque, Error-Control Techniques for Digital Communication, New York : Wiley, 1985
  7. T. R. N. Rao and E. Fujiwara, Error Control Coding for Computer Systems. Englewood Cliffs, NJ : Prentice-Hall, 1989
  8. S. B. Wicker and V. K. Bhargava, Reed-Solomon Codes and Their Applications, IEEE Press, 1994
  9. J. H. Jeng and T. K. Truong, 'On decoding of both errors and erasures of a Reed-Solomon code using an inverse-free Berlekamp-Massey algorithm,' IEEE Trans. Commun., vol. 47, pp. 1488-1494, Oct. 1999 https://doi.org/10.1109/26.795817
  10. H. J. Kang and I. C. Park, 'A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure,' in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS' 2002), May 2002, pp. 3180-3183 https://doi.org/10.1109/ICASSP.2002.1005363
  11. H. M. Hsu and C. L. Wang, 'An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm,' IEEE Trans. Circuits Syst. Video Technol., vol. 7, pp. 864-871, Dec. 1997 https://doi.org/10.1109/76.644066
  12. D. V. Sarwate and N. R. Shanbhag, 'High-speed architectures for Reed-Solomon decoders,' IEEE Trans. VLSI Syst., vol. 9, pp. 641-655, Oct. 2001 https://doi.org/10.1109/92.953498
  13. M. A. A. Ali, A. Abou-El-Azm, and M. F. Marie, 'Error rates for non-coherent demodulation FCMA with Reed-Solomon codes in fading satellite channel,' in Proc. IEEE Vehicular Techn. Conf. (VTC'99), vol. 1, 1999, pp. 92-96 https://doi.org/10.1109/VETEC.1999.778025
  14. T. K. Matsushima, T. Matsushima, and S. Hirasawa, 'Parallel architecture for high-speed Reed-Solomon codec,' in Proc. IEEE Int. Telecommun. Symp. (ITS;98), vol. 2, 1998, pp. 468-473 https://doi.org/10.1109/ITS.1998.718439
  15. M. K Song, E. B. Kim, H. S. Won and M. H. Kong, 'Architecture for decoding adaptive Reed-Solomon codes with variable block length,' IEEE Trans. Consumer Elec., vol. 48, pp. 631-637, Aug. 2002 https://doi.org/10.1109/TCE.2002.1037052
  16. C. T. Huang and C. W. Wu, 'VLSI design of a high speed pipelined Reed-Solomon CODEC,' in Proc. Int. Symp. Multi-Technology inform. Processing (ISMIP), Dec. 1996, pp. 517-522
  17. H. H. Lee, M. L. Yu and L. Song, 'VLSI design of Reed-Solomon decoder architectures,' in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS' 2000), vol. 5, May 2000, pp. 705-708 https://doi.org/10.1109/ISCAS.2000.857589
  18. H. H. Lee, 'Modified Euclidean algorithm block for high-speed Reed-Solomon decoder,' IEE Electronics Letters, vol. 37, pp. 903-904, july 2001 https://doi.org/10.1049/el:20010628
  19. H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen and I. S. Reed, 'A VLSI design of a pipeline Reed-Solomon decoder,' IEEE Trans. Comput., vol. C-34, pp. 393-403, May 1985 https://doi.org/10.1109/TC.1985.1676579
  20. H. M. Shao and I. S. Reed, 'On VLSI design of a pipeline Reed-Solomon decoder using systolic arrays,' IEEE Trans. Comput., vol. 37, pp. 1273-1279, Oct. 1988 https://doi.org/10.1109/12.5988
  21. X. Yuanxin, X. Fang, Y. Qindong, Q. Peiliang, and W. Kuang, 'A new VLSI design for decoding Reed-Solomon codes based on ASIP,' in Proc. Int. ASIC Conference, 2001, pp. 448-451 https://doi.org/10.1109/ICASIC.2001.982597
  22. K. Iwamura, Y. Dohi, and H. Imai, 'A design of Reed-Solomon decoder with systolic-array structure,' IEEE Trans. Comput., vol. 44, pp. 118-122, Jan. 1995 https://doi.org/10.1109/12.368005
  23. M. Martina, G. Masera, G. Piccinini, F. Vacca, and M. Zamboni, 'VLSI Reed Solomon decoder architecture for networked multimedia applications,' in Proc. IEEE Int. ASIC/SOC Conference, 2001, pp. 347-351 https://doi.org/10.1109/ASIC.2001.954725
  24. J. H. Baek, J. Y. Kang and Myung H. Sunwoo, 'Design of a high-speed Reed-Solomon decoder,' in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'2002), May 2002, pp. 793-796 https://doi.org/10.1109/ISCAS.2002.1010823