References
- ETRI J. v.23 no.3 Efficient Path Delay Test Generation for Custom Designs Kang, S.;Underwood, B.;Law, W.;Konuk, H.
- Proc. of IEEE VLSI Test Symposium Built-in Self Testing of Sequential Circuits Using Precomputed Test Sets Iyengar, V.;Charabarty, K.;Murray, B.T.
- J. Electron. Tet. Theory Applicat. v.15 Deterministic Builtin Pattern Generation for Sequential Circuits Iyengar, V.;Charabarty, K.;Murray, B.T.
- Proc. of Int'l Test Conf. Test Vector Decompression via Cyclical Scan Cahins and its Application to Testing Core-Based Design Jas, A.;Touba, N.A.
- IEEE Trans. Inform. Theory v.IT-12 Run-Length Encoding Golomb, S.W.
- IBM J. of Research & Development v.18 Image Data Compression by Predictive Coding, Part Ⅰ: Prediction Algorithm Kobayashi, H.;Bahl, L.R.
- IEEE Trans. Computer-Aided Design of Integrated Circuits and Syst. v.20 no.3 System-on-a-Chip Test Data Compression and Decompression Architectures Based on Golomb Codes Chandra, A.;Chakrabarty, K.
- Proc. of IEEE Int'l Conf. on Electronics, Circuits and Systems (ICECS 2001) An Efficient Test Vector Compression Technique Based on Geometric Shapes al Zahir, S.;El-Maleh, A.;Khan, E.
- IEEE Trans. Comput. ATPG for Heat Dissipation Minimization during Test Application Wang, S.;Gupta, S.K.
- Proc. of VLSI Test Symposium A Test Vector Inhibiting Technique for Low Energy BIST Design Girad, P.;Guiller, L.;Landrault, C.;Pravossoudovitch, S.
- IEEE Trans. Computer-Aided Design of Integrated Circuits and Syst. v.17 no.12 Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits during Test Application Dabhokar, V.;Chakravarty, S.;Pomeranz, I.;Reddy, S.M.
- Proc. Of IEEE/ACM Design Automation Conf.(DAC) Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip Chandra, A.;Chakrabarty, K.
- Electronics Lett. v.37 no.24 Simultaneously Reduction in Volume of Test Data and Power Dissipation for Systems-on-a-Chip Rosinger, P.;Gonciari, P.T.;Al-Hashimi, B.M.;Nicolici, N.
- Proc. of IEEE Symposium on VLSI(ISVLSI) Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering Ghosh, S.;Basu, S.;Touba, N.A.
- Proc. of IEEE VLSI Test Symposium Static Compaction Techniques to Control Scan Vector Power Dissipation Sankaralingam, R.;Oruganti, R.R.;Touba, N.A.
- Proc. of Int'l Conf. Computer-Aided Design Test Set Compaction Algorithms for Combinational Circuits Hamzaoglu, I.;Patel, J.H.