References
- J. Huang and M. Hagiwara , A Multi-Winner Associative Memory, IEICE Trans. INF & SYST., vol. E82-D, No.7, pp. 1117-1124, July 1999.
- T. Shibata and T. Ohmi, Neuron MOS Binary-Logic Integrated Circuits, IEEE Trans. on Electron Devices, Vol 40, No.3, pp. 570-576, March 1993 https://doi.org/10.1109/16.199362
- P. Hasler, T. Stanford, B.A. Minch, and C. Diorio, An Autozeroing Floating Gate Second-Order Section, Proceedings of IEEE International Symposium on Circuits and Systems, Monterey, 1998
- R. R. Harison, P. Hasler, and B.A. Minch, Floating-gate CMOS analog memory cell array, Proceedings of IEEE International Symposium on Circuits and Systems. Monterey, 1998.
- Richard J. McPartland and Ranbir Singh, 1.25Volt, Low Cost, Embedded Flash Memory for Low Density Applications, IEEE 2000 Symposium on VLSI Circuits Digest of Technical Papers
- John F. Dickson, 'On-chip highvoltage generation in MNOS integrated circuits using and improved voltage multiplier technique,' IEEE J. Solid-State Circuits, vol. 11. pp. 374-378, June 1976 https://doi.org/10.1109/JSSC.1976.1050739
- R. Jacob Baker, Harry W. Li , and David E. Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press, Piscataway, 1997
- Jahanshir J. .Javanifard.. and Marc E. Landgraf. ' Charge pump circuit for providing multiple output voltages for flash memory,' U.S. Patent 5483486, Jan. 1996
- Kazuhiko Fukushima. Atsuo Yamaguchi, 'Charge pump circuit,' U.S. Patent 6107864, Aug. 2000.