시간 제약 조건하에서의 최적 선택 공급 전압을 위한 전력 감소 스케줄링

Reducing Power Consumption of a Scheduling Algorithm for Optimal Selection of Supply Voltage under the Time Constraint

  • 최지영 (제천기능대학 정보통신설비과) ;
  • 김희석 (청주대학교 전자공학과)
  • 발행 : 2002.11.01

초록

본 논문은 시간 제약 조건하에서의 최적 선택 공급 전압을 위한 전력 감소 스케줄링 알고리듬을 제안한다. 전력감소 스케줄링에서는 전력소비를 줄이기 위해 가변 전압 레벨을 이용해 최적 공급 전압을 선택 휴리스틱 방법으로 연산을 수행하여 제어 스텝을 결정한다. 그리고 최적 선택 공급 전압 바인딩에서는 그래프 컬러링 기법을 이용해 레지스터 상의 전력 소비의 주원인인 스위칭 활동을 최소화한다. 상위 수준 벤치마크 예제를 이용한 실험으로부터 우리는 최적 선택 공급 전압을 이용한 제안한 알고리듬이 획일화된 단일 전압을 이용한 알고리듬보다 전력 소비를 줄이는데 효율적임을 보인다.

This paper proposes a reducing power consumption of a scheduling algorithm for optimal selection of supply voltage. In scheduling of reduction power consumption, we determine the control steps of operations to be executed by exploiting the possibility of using variable voltage levels to reduce power consumption. In the optimal selection of supply voltage binding, we minimize the main factor of the power consumption of the switching activity on the registers using a graph coloring technique. From a set of experiments using high-level benchmark examples, we show that the proposed algorithm prefer to use optimal selection supply voltages rather than uniformed single voltage is effective in reducing power consumption.

키워드

참고문헌

  1. IEEE Trans. CAD v.7 no.8 Behavioral to Structural Translation in a Bit-Serial Silicon Compiler R.Hartley
  2. IEEE Proceedings v.83 no.4 Minimizing Power Consumption in Digital CMOS Circuits A.Chandrakasan;R.Brodersen
  3. J. Solid-State Circuits v.27 no.4 Low-Power CMOS Digital Design A.Chandrakasan(et al.)
  4. Proc. 29th DAC Estimation of Average Switching Activity in Combination and Sequential Circuits A.Ghosh
  5. Proc. European DAC Power Estimation of High-Level Synthesis P.Landman
  6. Proc. ICCAD HYPER-LP: A System fo Power Minimization Using Architecture Transformation A.Chandarksan(et al.)
  7. Proc. 32nd DAC Power-Profiler : Optimizing ASICs Power Consumption at the Behavioral Level R.Marin
  8. Proc. 32nd DAC Register Allocation and Binding for Low Power J.Chang
  9. Proc. IEEE v.83 Minimizing power consumption in digital CMOS circuit A.chandraksan;R.Brodersen
  10. IEEE Trans. Computer Aided design v.14 Optimizing power using transformations A. chandraksam;M;Potkonjak;R.Mehra;J.Rabaey;Brodersen
  11. Proc. Int. Symp. Low-Power Design Simultaneous scheduling binding for low power minimization during microarchitecture synthesis A.Dasgupta;R.Karri
  12. Proc. IEEE design Automation conf. Behavioral synthesis for low power A.Raghnathan;N.K.Jha
  13. Proc. Int. Symp. Low Power Design High-level synthesis techiques for reducing the activity of functional unit E.Musoll;J.Cortadella
  14. Technical Report 397-28, University of California;Irvine A Design Methodology for Behavioral Level Power Exploration : Implementation and Experiments H.Singh;D.D.Gajski
  15. IEEE Trans. VLSI Sys. v.5 Energy minimization using mutiple supply voltage J.M.Chang;M.Pedram
  16. ACM Trans. Design Automat. Electron. Syst. v.2 no.3 Datapath scheduling with multipe supply voltages and level converters M.C.Johnson;K.Roy