Fault Diagnosis Algorithm for Dual Port Memories

이중 포트 메모리를 위한 고장 진단 알고리듬

  • Park, Han-Won (Dept.of Electric Electronics Engineering, Yonsei University) ;
  • Gang, Seong-Ho (Dept.of Electric Electronics Engineering, Yonsei University)
  • 박한원 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2002.03.01

Abstract

As dual port RAMs are widely used in the various applications, the need for an efficient algorithm to diagnose faults in dual port RAMs is increased. In this paper we propose an efficient algorithm that can diagnose all kinds of faults in dual port RAMs. In addition, the new algorithm can distinguish various fault models and locate the position related to each fault. Using the new algorithm, fault diagnosis for dual port RAMs can be performed efficiently and the performance evaluation with previous approaches proves the efficiency of the new algorithm.

현재 다양한 분야에서 이중 포트 메모리의 사용이 증가함에 따라서 이중 포트 메모리의 고장을 진단하기 위한 효율적인 고장 진단 알고리듬의 필_도성이 증대되고 있다. 따라서 본 논문에서는 이중 포트 메모리에서의 효율적인 고장 진단 알고리듬을 제시하여 이중 포트 메모리에서 발생하는 거의 모든 종류의 고장에 대한 진단을 가능하게 한다. 또한 진단 과정에서 착오를 일으키지 않고 다양한 고장 모델을 구별하며 고장과 관련된 위치를 정확하게 확인하는 것이 가능하다. 새로운 진단 알고리듬을 사용함으로서 이중 포트 메모리에서의 고장 진단과정은 효과적으로 수행될 수 있으며 이전의 다른 연구들과의 성능 평가를 통해 효율성을 확인할 수 있다.

Keywords

References

  1. J. Otterstedt, D. Niggemeyer, T.W. Williams, 'Detection of CMOS address decoder open faults with March and pseudo random memory tests,' Test Conference, 1998. Proceedings., International, 1998, Page(s): 53-62 https://doi.org/10.1109/TEST.1998.743137
  2. Sying-Jyan Wang, Chen-Jung Wei, 'Efficient built-in self-test algorithm for memory,' Asian Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth, 2000, Page(s): 66-70 https://doi.org/10.1109/ATS.2000.893604
  3. Chih-tsun Huang, Jing-Reng Huang, 'A programmable built-in self-test core for embedded memories,' Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and Soth Pacific, 2000, Page(s): 11-12 https://doi.org/10.1109/ASPDAC.2000.835054
  4. M. Azimane, A.L. Ruiz, 'New short and efficient algorithm for testing random-access memories,' Electronics, Circuits and Systems, 1998 IEEE International Conference on, Volume: 1, 1998, Page(s): 541-544 https://doi.org/10.1109/ICECS.1998.813380
  5. V. Kim, T. Chen, 'Assessing defect coverge of memory testing algorithms,' VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on, 1999, Page(s): 340-341 https://doi.org/10.1109/GLSV.1999.757450
  6. H. Yokoyama, H. Tamamoto, Wen Xiaoqing, 'Built-in random testing for dual-port RAMs,' Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on, 1994, Page(s): 2-6 https://doi.org/10.1109/MTDT.1994.397206
  7. T. Matsumura, 'An efficient test method for embedded mult-port RAM with BIST circuitry,' Memory Technology, Design and Testing, 1995., Records of the 1995 IEEE International Workshop on, 1995, Page(s): 62-67
  8. A.J. van de Goor, S. Hamdioui, 'Fault models and tests for two-port memories,' VLSI Test Symposium, 1998. Proceedings. 16th IEEE, 1998, Page(s): 401-410 https://doi.org/10.1109/VTEST.1998.670898
  9. M.F. Chang, W.K. Fuchs, J.H. Patel, 'Diagnosis and repair of memory with coupling faults,' computers, IEEE Transactions on, volume38, No.4, April 1989, Page(s): 493-500 https://doi.org/10.1109/12.21142
  10. Lin Shen, B.F. Cockburn, 'An optimal march test for locating faults in DRAMs,' Memory Testing, 1993., Records of the 1993 IEEE International Workshop on, 1993, Page(s): 61-66 https://doi.org/10.1109/MT.1993.263148
  11. Chin Tsung Mo, Chung Len Lee, Wen Ching Wu, 'A self-diagnostic BIST memory design scheme,' Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on, 1994, Page(s): 7-9 https://doi.org/10.1109/MTDT.1994.397205
  12. C.F. Wu, C.T. Huang, 'Error catch and analysis for semiconductor memories using march tests,' Computer-Aided Design, 2000. ICCAD 2000. Digest of Technical Papers, 2000 IEEE/ACM International Conference on, 2000, Page(s): 468-471 https://doi.org/10.1109/ICCAD.2000.896516
  13. T.J. Bergfeld, D. Niggemeyer, E.M. Rudnick, 'Diagnostic testing of embedded memories using BIST,' Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, 2000, Page(s): 305-309 https://doi.org/10.1109/DATE.2000.840288
  14. J. Zhao, S. Irrinki, M. Puri, F. Lombardi, 'Detection of inter-port faults in multi-port static RAMs,' VLSI Test Symposium, 2000. Proceedings. 18th IEEE, 2000, Page(s): 297-302 https://doi.org/10.1109/VTEST.2000.843858
  15. S. Harndioui, A.J. Van De Goor, 'Address decoder faults and their tests for two-port memories,' Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on, 1998, Page(s): 97-103 https://doi.org/10.1109/MTDT.1998.705954
  16. A.J. van de Goor, Testing Semiconductor Memories: Theory and practice, J. Wiley & Sons, 1991