대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

부분요소 등가회로를 이용한 시간영역에서의 인터커넥트 모델링 연구

Modeling Interconnect Wiring using the Partial Element Equivalent Circuit Approach in Time Domain

  • 박설천 (인하대학교 공과대학 전자전기공학부) ;
  • 윤석인 (인하대학교 공과대학 전자전기공학부) ;
  • 원태영 (인하대학교 공과대학 전자전기공학부)
  • 발행 : 2002.01.01
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초록

본 논문에서는 대략적인 PEEC 방법에 대해 논의 하고, 도선에 대하여 PEEC 등가회로를 구성하였으며, 주어진 등가회로로 부터 시스템의 행렬을 구하고, 이 행렬을 수치 해석적인 방법을 이용한 시뮬레이션을 수행하여 노드에서의 전압과 전류를 구하였다. PEEC 등가 회로를 구성하기 위해서, PEEC 등가 회로를 구성하는 성분(R, L, C)을 유한 요소법(finite element method)을 이용한 시뮬레이터를 이용하여 추출하였으며, 생성된 등가 회로에 대한 과도 해석을 수행하였다.

In this Paper, we discuss the PEEC method and construct the PEEC equivalent circuit of the test structure and construct the system matrix, which was simulated by numerical analysis. And we got node voltages and currents. Constructing the equivalent circuit, we extracted the parasitic parameter(R, L, C)using the simulator, which is based on finite element method, hence we could simulate the transient analysis.

키워드

참고문헌

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