The Transactions of the Korean Institute of Electrical Engineers C (대한전기학회논문지:전기물성ㆍ응용부문C)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

Optimization of Double Polishing Pad for STI-CMP Applications

STI-CMP 적용을 위한 이중 연마 패드의 최적화

  • 박성우 (대불대학교 전기공학과 석사) ;
  • 서용진 (아남 반도체 FAB 사업부.) ;
  • 김상용 (대불대학교 전기공학과.)
  • Published : 2002.07.01
Download PDF
⟨ Previous Next ⟩

Abstract

Chemical mechanical polishing (CMP) process was required for the global planarization of inter-metal dielectric(IMD), inter-level dielectric (ILD) layers of multi-layer interconnections. In this paper, we studied the characteristics of polishing pad, which can apply shallow trench isolation (STI)-CMP process for global planarization of multi-level interconnection structure. Also, we investigated the effects of different sets of polishing pad, such as soft and hard pad. As an experimental result, hard pad showed center-fast type, and soft pad showed edge-fast type. Totally, the defect level has shown little difference, however, the counts of scratch was detected less than 2 on JR111 pad. Through the above results, we can select optimum polishing pad, so we can expect the improvements of throughput and device yield.

Keywords

References

  1. Joseph M. steigerwald. Shyam P. Murarka, Ronald J. Gutmann, Chemical Mechanical Planarization of Microelectronic Materials, John wiley & sons, INC, 1997
  2. S. H. Bath, R. Legegett, A. Maury, K. Manning, and R. Tolles, 'Planarizing Interlevel Dielectrics by Chemical Mechanical Polishing', Solid State Tech. pp. 87-91, May 1992
  3. M. Lin, C. Y. Chang, D. C. Liao, B. Wang, and Allen Henderson, 'Improved STl CMP Technology for micro-scratch issue', Proceeding of CMP-MIC, pp. 322-326, 1999
  4. P. Sallagoity, F. Gaillard, M. Rivoire, M. Paoli and F. Martin, 'STI process steps for sub-quarter micron CMOS', Microelectron. Reliability, Vol. 38, No.2, pp. 271-276, 1998 https://doi.org/10.1016/S0026-2714(97)00166-2
  5. K. Smekalin, 'CMP dishing effects in shallow trench isolation', Solid State Technology, pp. 187-194, 1997
  6. Yong-Jin Seo, Woo-Sun Lee, Sang-Yong Kim, Jin-Sung Park, Eui-Goo Chang, 'Optimization of Post-CMP Cleaning Process for Elimination of CMP Slurry Induced Metallic Contaminations', Journal of Materials Science : Materials in Electronics, Vol. 12, No.7, pp. 411-415, 2001 https://doi.org/10.1023/A:1011242900843
  7. 이우선, 서용진, 김상용, 장의구, 'STI-CMP 공정의 질화막 잔존물 및 패드 산화막 손상에 대한 연구', 대한전기학회 논문지, Vol. 50, No. 9, pp. 438-443, 2001
  8. 박성우, 정소영, 박창준, 이경진, 김기욱, 김철복, 김상용, 서용진, 'CMP 공정의 설비요소가 공정 결함에 미치는 영향', 대한전기학회 논문지, Vol. 51, No. 5
  9. P. Singer, 'Chemical-Mechanical Polishing : A New Focus on Consumable', Semiconductor International, pp. 48-53, Feb, 1994
  10. I. Kim, K. Murella, and J. Schlueter, 'A detailed look at oxide CMP pad to pad consistency,' CMP-MIC proceeding, pp. 335-338, 1997
  11. I. All and S. R. Roy, 'Pad conditioning in interlayer dielectric CMP,' Solid State Technology, pp. 185-191, 1997