Journal of Korean Institute of Industrial Engineers (대한산업공학회지)

Korean Institute of Industrial Engineers (대한산업공학회)
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Simulated Annealing for Reduction of Defect Sensitive Area Through Via Moving

Via 이동을 통한 결함 민감 지역 감소를 위한 시뮬레이티드 어닐링

  • Lee, Seung Hwan (Department of Computer Science and Industrial Systems Engineering, Yonsei University) ;
  • Sohn, So Young (Department of Computer Science and Industrial Systems Engineering, Yonsei University)
  • 이승환 (연세대학교 컴퓨터과학.산업시스템공학과) ;
  • 손소영 (연세대학교 컴퓨터과학.산업시스템공학과)
  • Published : 2002.03.31
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Abstract

The semiconductor industry has continuously been looking for the ways to improve yield and to reduce manufacturing cost. The layout modification approach, one of yield enhancement techniques, is applicable to all design styles, but it does not require any additional resources in terms of silicon area. The layout modification method for yield enhancement consists of making local variations in the layout of some layers in such a way that the critical area, and consequently the sensitivity of the layer to point defects, is reduced. Chen and Koren (1995) proposed a greedy algorithm that removes defect sensitive area using via moving, but it is easy to fall into a local minimum. In this paper, we present a via moving algorithm using simulated annealing and enhance yield by diminishing defect sensitive area. As a result, we could decrease the defect sensitive area effectively compared to the greedy algorithm presented by Chen and Koren. We expect that the proposed algorithm can make significant contributions on company profit through yield enhancement.

Keywords

References

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