JSTS:Journal of Semiconductor Technology and Science

  • 제1권4호
  • /
  • Pages.216-231
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  • 2001
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Antifuse Circuits and Their Applicatoins to Post-Package of DRAMs

  • Wee, Jae-Kyung (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.) ;
  • Kook, Jeong-Hoon (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.) ;
  • Kim, Se-Jun (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.) ;
  • Hong, Sang-Hoon (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.) ;
  • Ahn, Jin-Hong (Advanced Design Technology Team, Memory R&D, Hynix Semiconductor Inc.)
  • 발행 : 2001.12.01
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초록

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

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참고문헌

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