참고문헌
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- IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE, June 1989
- P. T. Wagner, Interconnect Testing with Boundary Scan, Proceedings International Test Conference, 1987, pp. 52-57
- S. Park, A new Complete Diagnosis Patterns for Wiring Interconnects, ACM/IEEE Design Automation, pp. 203-208, 1996 https://doi.org/10.1145/240518.240556
- K. Lofstrom, Early Capture For Boundary Scan Timing Measurements, Proceedings of IEEE International Test Conference, pp. 417-422, 1996 https://doi.org/10.1109/TEST.1996.557045
- J. Shin, H. Kim, S. Kang, At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks, Proceedings of European Design and Test Conference, pp.473-477, 1998 https://doi.org/10.1109/DATE.1999.761168
- W. Ke, Backplane Interconnect Test in a Boundary Scan Environment, Proceedings of IEEE International Test Conference, pp. 717-724, 1996 https://doi.org/10.1109/TEST.1996.557130
- W. Ke, Hybrid Pin Control Using Boundary Scan and Its Applications, Proceedings of IEEE International Asian Test Symposium, Taiwan, 1996 https://doi.org/10.1109/ATS.1996.555135
- P. Gillis, F. Woytowich, K. McCauley and U. Baur, Delay Test of Chip I/Os using Lssd Boundary Scan, Proceedings of IEEE International Test Conference, 1998 https://doi.org/10.1109/TEST.1998.743140
- L. Whetsel, An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores, Proceedings of IEEE International Test Conference, PP. 69-78, 1997 https://doi.org/10.1109/TEST.1997.639596
- B. Nadeau-Dostie, J-F. Cote, H. Hulvershorn and S. Pateras, An Embedded Technique For At-Speed Interconnect Testing, Proceedings of IEEE International Test Conference, pp.431-438, 1999 https://doi.org/10.1109/TEST.1999.805765
- Synopsys document on Adding Boundary Test Circuitry