참고문헌
-
A. Nishida, E. Murakami and S. Kimura, 'Characteristics of Low-Energy BF2- or As-Implanted Layers and Their Effect on the Electrical Performance of 0.l5-
${\mu}m$ MOSFET's,' IEEE Trans. Electron Devices, Vol. 45, No. 3, pp. 701-709, March1998 https://doi.org/10.1109/16.661231 -
M. Rodder, S. Hattangady, N. Yu, W. Shiau, P. Nicollian, T. Laaksonen, C.P. Chao, M. Mehrotra, C. Lee, S. Curtaza and S. Aur, 'A 1.2V, 0.1
${\mu}m$ Gate Length CMOS Technology: Design and Process Issues,' in IEDM Tech. Dig., pp. 623-626, San Francisco, USA, December 1998 https://doi.org/10.1109/IEDM.1998.746435 -
Y-H. Kim, S-K. Chang, S-S. Kim, J-G. Choi, S-H. Lee, D-H. Hahn and H-D. Kim, 'Characteristics of Dual Polymetal (W/WNX/Poly-Si) Gate CMOS for 0.1
${\mu}m$ DRAM Technology,' in Ext. Abst. of Int. Conf. on SSDM, pp. 12-13, Tokyo, Japan, September 1999 -
H. Wakabayashi, T. Yamamoto, Y. Saito, T. Ogura M. Narihiro, K. Tsuji, T. Fukai, K. Uejima, Y. Nakahara, K. Takeuchi, Y. Ochiai, T. Mogami and T. Kunio, 'A 0.1-
${\mu}m$ CMOS Device with a 40-nm Gate Sidewall and Multilevel Interconnects for System LSI,' in Symp. on VLSI Tech., pp. 107-108, Kyoto, Japan, June 1999 https://doi.org/10.1109/VLSIT.1999.799363 - N. Lindert, M. Yoshida, C. Wann and C. Hu, 'Comparison of GIDL in p+-poly PMOS and n+-poly PMOS Devices,' IEEE Electron Device Lett., Vol. 17, No. 6, pp. 285-287, June 1996 https://doi.org/10.1109/55.496459
-
R. Ghodsi, S. Sharifzadeh and J. Majjiga, 'Gate-Induced Drain-Leakage in Buried-Channel PMOS - A Limiting Factor in Development of Low-Cost, High-Performance 3.3-V, 0.25-
${\mu}m$ Technology,' IEEE Electron Device Lett., Vol. 19, No. 9, pp. 354-356, September 1998 https://doi.org/10.1109/55.709642 - K-W. Kim, C-S. Choi and W-Y. Choi, 'Analysis of a Novel Elevated Source Drain MOSFET with Reduced Gate-Induced Drain-Leakage Current,' in 2000 Hongkong Electron Device Meeting, pp. 36-39, Hong Kong, June 2000 https://doi.org/10.1109/HKEDM.2000.904210
- Technology Modeling Associate, Inc. : TSUPREM-4, Two-Dimensional Process Silmulation Program, Version 6.5, User's Manual, Sunnyvale, California, May 1997
-
J. Tanaka, S. Kimura, H. Noda, T. Toyabe and S. Ihara, 'A Sub-0.1-
${\mu}m$ Grooved Gate MOSFET with High Immunity to Short-Channel Effects,' in IEDM Tech Dig., pp. 537-540, Washington DC, USA, December 1993 https://doi.org/10.1109/IEDM.1993.347293 - W-H. Lee, Y-J. Park and J-D. Lee, 'Gate Recessed (GR) MOSFET with Selectively Halo-Doped Channel and Deep Graded Source/Drain for Deep Submicron CMOS,' in IEDM Tech Dig., pp. 135-138, Washington D.C., USA, December 1993 https://doi.org/10.1109/IEDM.1993.347381
-
J. Lyu, B-G. Park, K. Chun and J-D. Lee, 'A Novel 0.1
${\mu}m$ MOSFET Structure with Inverted Sidewall and Recessed Channel,' IEEE Electron Device Lett., Vol. 17, No. 4, pp. 157-159, April 1996 https://doi.org/10.1109/55.485159 - J-H. Lee, H-C. Shin, J-J. Kim, C-B. Park and Y-J. Park, 'Partially Depleted SOI NMOSFET's with Self-Aligned Polysilicon Gate Formed on the Recessed Charmel Region,' IEEE Electron Device Lett., Vol. 18, No. 5, pp. 184-186, May 1997 https://doi.org/10.1109/55.568756
- H. Hwang K-S. youn, J-G. Ahn, D. Yang, J-H. Ha, Y-J. Huh, J-W. Park, J-J. Kim and W-S. Kim, 'Performance and Reliability Optimization of Ultra Short Channel CMOS Device for Giga-bit DRAM Applications,' in IEDM Tech Dig., pp. 435-438, Washington D.C., USA, December 1995 https://doi.org/10.1109/IEDM.1995.499232
- Technology Modeling Associate, Inc. : MEDICI, Two-Dimensional Device Simulation Program, Version 4.0, User's Manual, Sunnyvale, California, October 1997
- T.Y. Chan, J. Chen, P.K. Ko and C. Hu, 'The Impact of Gate-Induced Drain Leakage Current on MOSFET Scaling,' in IEDM Tech. Dig., pp. 718-721, Washington D.C., USA, December 1987