융합신호처리학회논문지 (Journal of the Institute of Convergence Signal Processing)

한국융합신호처리학회 (The Korea Institute of Convergence Signal Processing)
권호 표지

전류모드 CMOS를 이용한 GF(P$^{m}$ )상의 셀 배열 승산기

Cell array multiplier in GF(p$^{m}$ ) using Current mode CMOS

  • 최재석 (인덕대학 메카트로닉스과)
  • 발행 : 2001.07.01
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⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 GF($P^{m}$ )상에서의 새로운 승산 알고리듬과 승산기 구성법을 나타내었다. 유한체 상에서의 두 원소에 대한 승산공식을 유도하였고 유도된 수식에 의해 승산기를 구성하였다. 적용예로 GF(3) 승산 모듈과 덧셈 모듈을 전류 모드 CMOS 기법을 적용하여 구현하였다. 이러한 모듈을 기본 모듈로 사용하여 GF(3$^{m}$ )승산기를 설계하였고 SPICE를 통하여 검증하였다. 제시된 승산기는 규칙적인 셀 구조를 사용하였고 단순히 규칙적인 내부 결선으로 구성된다. 따라서, 유한체 상에서 차수가 m 차로 증가하는 승산에 대해서도 간단히 확장이 가능하다.

In this paper, a new multiplication algorithm which describes the methods of constructing a multiplierover GF(p$^{m}$ ) was presented. For the multiplication of two elements in the finite field, the multiplication formula was derived. Multiplier structures which can be constructed by this formula were considered as well. For example, both GF(3) multiplication module and GF(3) addition module were realized by current-mode CMOS technology. By using these operation modules the basic cell used in GF(3$^{m}$ ) multiplier was realized and verified by SPICE simulation tool. Proposed multipliers consisted of regular interconnection of simple cells use regular cellular arrays. So they are simply expansible for the multiplication of two elements in the finite field increasing the degree m.

키워드

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