Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Estimation of Short Circuit Power in Static CMOS Circuits

정적 CMOS 회로의 단락 소모 전력 예측 기법

  • Published : 2000.11.01
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Abstract

This paper presents a simple method to estimate short-circuit power dissipation for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution. The proposed analytical expressions can be easily applied in such applications as power estimation even when the current expression is changed.

본 논문은 정적 CMOS 회로의 단락전류로 인한 전력 소모을 구하기 위한 간단한 방법을 제시한다. 단락전류식은 게이트와 드레인 사이에 존재하는 커플링 커패시턴스의 영향을 고려하여 실제 전류 파형의 극점을 정확하게 보간함으로써 유도하였다. 트랜지스터의 출력 파형을 조사한 후 모형화한 전류 수식을 기반으로 CMOS 회로의 지연 시간을 예측하기 위한 거시모형과 수식들을 제안하였다. 제안된 방법은 시뮬레이션을 통하여 현재의 기술 동향 특성인 신호 천이시간과 부하 커패시턴스가 감소하는 경우에 대해 이전의 연구보다 더욱 정확하고 신속히 예측할 수 있음을 보였다. 또한 제안된 거시모형은 전류식이 변할지라도 전력 소모를 계산하는데 쉽게 적용이 가능하다.

Keywords

References

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