Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Circuit Simulation Model of Ferroelectric Capacitors and its AHDL Implementation

강유전체 캐패시터의 회로 시뮬레이션 모델과 이의AHDL 구현

  • Kim, Shi-Ho (Department of Semiconductor Science, Wonkwang University)
  • Published : 2000.10.01
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Abstract

We provided a model for accurately computing the Hysteresis characteristics of the ferrelectric thin film capacitors. This model is developed form the semi-empirical ferroelectric model based on the double well harmonic oscillator. We have seen that this model is consistent with physical analysis using the Preisach's hysteresis distribution. This model includes the parameters representing the slope of changing Hysteresis curves and the imprint of ferroelectric capacitors. Besides, we showed that this model could predict accurate sub-hystersis loop by the turning points when the polarities of applied voltage were changed before saturation. The simulation and measurement result showed that this model is well applicable to both PZT and SBT materials. This model has been described by AHDL and successfully implemented into Spectre simulator to provide circuit design environment of commercial CAD tools such as Cadence software.

본 연구에서는 강유전체의 이력 특성을 정밀하게 계산하기 위한 모델을 제공하였다. 본 모델은 2중 전위우물에 근거한 반경험적 분극 천이 모델에 기초하고 있으며 프라이사흐의 이력 함수의 분포 모델의 물리적 특성과도 잘 일치되고 있음을 보였다. 본 모델은 강유전체 이력 특성의 천이 경사도와 임프린트 특성을 고려하고 있으며 인가 전압의 극성이 바뀌는 경우에 발생되는 부 이력 경로에 대해서도 정확하게 분극 전하의 변화를 표현하고 있음을 보였다. 본 모델의 예측 결과는 PZT와 SBT의 두 종류의 강유전체에 대해서 측정 결과와 잘 일치하고 있음을 보였다. 또한, 본 모델을 AHDL 코드로 구현하여 스펙트레 시뮬레이터를 통하여 회로 설계를 할 수 있는 환경을 제공하였다.

Keywords

References

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