References
- Dr. Walter Y. Chen, 'DSL Simulation Techniques and Standards Development for Digital Subscriber Line Systems,' MACMILLAN TECHNOLOGY SERIES, 1998
- ANSI T1.413 ISSUE 2.
- John M. Cioffi, Vladimir Oksman , Thierry Pollet and Jacky S. Chow, 'Very-HighSpeed Digital Subscriber Lines,' IEEE Communications Magazine, April 1999
- KyungHa LEE, YoungHoon KIM and HyungJin CHOI, 'A New Symbol Timing Recovery for All-digital High Speed Symbol Synchronization,' IEICE Trans. Commun., vol. E80-B, NO.9 September 1997
- Erdal Panayirci, 'Timing Recovery for DSL Transceivers in the Presence of Residual Echo and Impulsive Noise,' IEEE Trans. on Commun., vol. 45. No.8, August 1997 https://doi.org/10.1109/26.618292
- W.C. Lindsey and C.M. Chie, 'A survey of digital phase-locked loops,' IEEE Proceedings, vol. 69, pp. 410-431, April 1981
- H.J. Choi, 'Synchronous Digital Communications,' Kyohaksa, Korea, 1995
- Dominique N. Godard, 'Passband Timing Recovery in an All-Digital Modem Receiver,' IEEE Trans. on Commun., vol. COM-26, No.5, May 1976
-
Fang Lu, Henry Samueli, Jiren Yuan and Christer Svensson, 'A 700-MHz 24-b Pipelined Accumulator in 1.2
${\mu}m$ CMOS for Application as a Numerically Controlled Oscillator,' IEEE J. Solid State Circuits, VOL. 28, NO.8, pp. 878-885, August 1993 https://doi.org/10.1109/4.231324 - DA VIC 1.2 Specification Part 8
- L-N. Lee, A. Shenoy and M.K. Eng, 'Digital signal processor-based programmable BPSK/QPSK/offset -QPSK modems,' Comsat Technical Review VOL. 19, Number 2, Fall 1989
- Gardner, 'Phaselock Techniques,' JOHN WILEY & SONS., 1979
- D. Fu and A. N. Willson, Jr. 'A High-Speed Processor for Digital Sine/Cosine Generation and Angle Rotation', 32nd Asilomar Conference, 1998 https://doi.org/10.1109/ACSSC.1998.750849
- D. A. Sunderland, R. A. Strauch, S. Wharfield, H. T. Peterson and C. R. Cole, 'CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Sprectrum Communications', IEEE J. Solid-State Circuits, vol. sc-19, pp. 497-505, Aug. 1984
-
H. T. Nicholas, III and H. Samueli, 'A 150 MHz direct digital frequency synthesizer in 1.25--
${\mu}m$ CMOS with -90 dBc spurious performance,' IEEE J. Solid-State Circuits, vol. 26, pp. 1959-1969, Dec. 1991 https://doi.org/10.1109/4.104190 -
Loke Kun Tan and Henry Samueli, 'A 200 MHz Quadrature Digital Synthesizer/Mixer in 0.8
${\mu}m$ CMOS', IEEE J. Solid-State Circuits, vol. 30, pp. 193-200, Mar. 1995 https://doi.org/10.1109/4.364432