Journal of the Institute of Electronics Engineers of Korea SC (전자공학회논문지SC)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Design of A CMOS Composite Cell Analog Multiplier

CMOS 상보형 구조를 이용한 아날로그 멀티플라이어 설계

  • Lee, Geun-Ho (Dept.of Electronics Information Engineering, Chonbuk National University) ;
  • Choe, Hyeon-Seung (Dept.of Electronics Information Engineering, Chonbuk National University) ;
  • Kim, Dong-Yong (Dept.of Electronics Information Engineering, Chonbuk National University)
  • 이근호 (전북대학교 전자정보공학부) ;
  • 최현승 (전북대학교 전자정보공학부) ;
  • 김동용 (전북대학교 전자정보공학부)
  • Published : 2000.03.01
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Abstract

In this paper, the CMOS four-quadrant analog multipliers for low-voltage low-power applications ate presented. The circuit approach is based on the characteristic of the LV(Low-Voltage) composite transistor which is one of the useful analog building blocks. SPICE simulations are carried out to examine the performances of the designed multipliers. Simulation results are obtained by 0.6${\mu}{\textrm}{m}$ CMOS parameters with 2V power supply. The LV composite transistor can easily be extended to perform a four-quadrant multiplication. The multiplier has a linear input range up to $\pm$0.5V with a linearity error of less than 1%. The measured -3㏈ bandwidth is 290MHz and the power dissipation is 373㎼. The proposed multiplier is expected to be suitable for analog signal processing applications such as portable communication equipment, radio receivers, and hand-held movie cameras.

본 논문에서는 저전압 저전력 시스템에 응용 가능한 CMOS 4상한 아날로그 멀티플라이어를 제안하였다. 제안된 멀티플라이어는 저전압에서 동작이 용이하며 아날로그 회로를 설계하는데 자주 이용되는 LV(Low-Voltage) 상보형 트랜지스터 방식의 특성을 이용하였다. LV 상보형 구조는 등가 문턱전압을 감소시킴으로서 회로의 동작전압을 감소시킬 수 있는 특징이 있다. 설계된 회로의 특성은 2V 공급전압하에서 0.6㎛ CMOS 공정파라미터를 갖는 HSPICE 시뮬레이션을 통하여 측정되었다. 이때 ±0.5V까지의 입력선형 범위내에서 선형성에 대한 오차는 1%미만이었다. 또한 -3㏈ 점에서의 대역폭은 290㎒, 그리고 전력소모는 373㎼값을 나타내었다.

Keywords

References

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