입력단 큐잉 방식의 ATM 스위치를 위한 효율적 셀 중재 방식에 관한 연구

An Effective Cell Scheduling Algorithm for Input Queueing ATM Switch

  • 김용웅 (LG정보통신 교환전송OBU전송연구소 다중통신실) ;
  • 원상연 (연세대학교 기계·전자공학부) ;
  • 박영근 (연세대학교 기계·전자공학부)
  • 발행 : 2000.01.01

초록

본 논문에서는 광대역 종합 정보 통신망을 구현하는데 필수적인 ATM 스위치의 방식 중 입력단 큐잉 방식에 적용할 수 있는 셀 중재 기법으로 입력된 큐잉방식에서의 HOL (Head-of-Line) 블록킹과 출력단 충돌을 개선하여 입력단과 출력단의 매칭이 최대가 되도록 하는 기법인 MUCS(Matrix Unit Cell Scheduler)를 개선한 WMUCS(Weighted Matrix Unit Cell Scheduler)를 제안한다. WMUCS는 MUCS의 장점인 단순한 알고리즘과 높은 처리율에 대한 특성은 그대로 지니면서 더 좋은 특성을 보여주었다. 그리고 MUCS의 문제점인 기근(starvation)현상을 보완하여 최대 처리율을 거의 100%로 출력단 큐잉 방식에 근접하는 뛰어난 결과를 얻어내었다. WMUCS의 성능 분석을 위해 소프트웨어로 시뮬레이션하였다. 가장 중요한 세 가지 파라미터는 최대 처리율과 평균 지연, 그리고 셀 손실률이다. 최대 처리율은 예상한대로 순수한 MUCS보다 다소 개선되었다. 평균 지연은 버스티 트래픽의 경우에 개선 효과가 뚜렷했다 셀 손실률도 WMUCS보다 우수한 수준이다.

In this paper, we propose a cell scheduling algorithm for input queueing ATM switch. The input queueing architecture is attractive for building an ultra-high speed ATM (Asynchronous Transfer Mode) switch. We proposea WMUCS (Weighted Matrix Unit Cell Scheduler) based on the MUCS which resolves HOL blocking and outputport contention. The MUCS algorithm selects an optimal set of entries as winning cells from traffic matrix (weightmatrix). Our WMUCS differs from the MUCS in generating weight matrices. This change solves the starvationproblem and it reduces the cell loss variance. The performance of the proposed algorithm is evaluated by thesimulation program written in C++. The simulation results show that the maximum throughput, the average celldelay, and the cell loss rate are significantly improved. We can see that the performance of WMUCS is excellentand the cost-effective implementation of the ATM switch using proposed cell scheduling algorithm.

키워드

참고문헌

  1. IEEE Communications Magazine ATM technology for corporate network Perter Newman
  2. IEEE Journal on Selected Areas in Communications-Computational and Artificial Intelligence in High Speed Networks v.12 no.2 Neural network-based ATM cell scheduling with queue length-based priority scheme Young-Keun Park;Gyunho Lee
  3. IEEE JSAC in communications v.6 Queueing in high-performance packet switching Michael G. Hluchyj;Mark J. Karol
  4. Design and development of cell queueing, processing and scheduling modules for iPOINT input-buffered ATM testbed H. Duan
  5. IEEE Communication Letters v.2 no.1 Matrix Unit Cell Scheduler (MUCS) for Input-Buffered ATM Switches H. Duan;J. W. Lockwood;S. M. Kang
  6. IEEE INFOCOM '97 A High-performance OC-12/OC-48 queue design prototype for input-bufferd ATM switch H. Duan;J. W. Lockwood;S. M. Kang
  7. IEEE Computer Magazine Finding the right ATM switch for the market R. Rooholamini;V. Cherkassky;M. Garver
  8. Computer Networks and ISDN Systems v.27 Survey of ATM Switch Architecture R. Y. Awdeh;H. T. Mouflah
  9. IEEE Journal on Selected Areas in Communications v.6 no.9 Queueing in high-performance packet switching M. G. Hluchyj;M. J. Karol
  10. IEEE Journal on Selected Areas in Communications v.8 no.8 Neural network design of a Banyan network controller T. X. Brown;K. H. Liu
  11. IEEE Trans. Communications v.39 no.5 The bypass queue in fast packet switching K. W. Sarkies
  12. An efficient scheduling algorithm for input-queuing ATM switches Bin Li;Mounir Ham;Xi-Ren Cao
  13. IEEE Trans. Communications v.COM-35 no.12 Input versus output queueing on a on a space-division packet switch M. J. Karol;M. G. Hluchyj;S. P. Morgan
  14. IEEE Trans. Parallel and Distributed Systems v.4 no.1 Symmetric cossar arbiters for VLSI communication switches Y. Tamir;H. c. Chi
  15. ACM Trans. on Computer Systems v.11 no.4 High Speed Switch Scheduling for Area Networks T. E. Anderson
  16. IEEE/ACM Trans. on Networking v.2 no.3 Two-Demensional Round-Robin Schedules for Packet Switches with Multiple Input Queues R. O. Lamarie;D. N. Serpanos
  17. IEEE Tran. VLSI Syst. A 3-dimensional queue (3DQ) for practical ultra-broadband input buffered ATM switches H. Duan;J. W. Lockwood;S. M. Kang