The Transactions of the Korea Information Processing Society (한국정보처리학회논문지)

Korea Information Processing Society (한국정보처리학회)
권호 표지

Performance Analysis and High-Speed Design of PSS-type Viterbi Algorithm in Gaussan and Burst Noise Channel

가우시안 및 버스트성 잡음채널에서의 PSS 방식 Viterbi Algorithm 성능분석과 고속 설계

  • 양형규 (경남대학교 산전전공학부) ;
  • 정지원 (한국해양대학교 전파공학과)
  • Published : 2000.06.01
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, e analyze the performance of the PSS-type Viterbi decoder which can reduce calculations and power consumption using the Monte Carlo simulations. Gaussian and burst noise channels are considered in this simulation, and we achieve that convolutional interleaver can reduce complexity and power consumption in burst noise channel. In order to implement the high-speed PSS-type Viterbi decoder, the architectures of decoder are presented, and we implemented the PSS-type Viterbi decoder for r=1/2, k=3 using the VHDL tool, and prove the decoding process.

Keywords

References

  1. SUN PING, YAO YAN AND CHOKGXI FENG, 'An Effective Simplifying Scheme for Viterbi Decoder.' IEEE Trans. Commum.,Vol.39, No.1, January 1991 https://doi.org/10.1109/26.68266
  2. S. KuboLa, K. Ohtani, and S Kata. 'High~Speed and High-Coding-Gain Viterbi Decoder with Low Power Consumption Employing SST scheme,' Electron. Lett., Vol.22, No.9, pp.491, Apr 1986 https://doi.org/10.1049/el:19860334
  3. Coates, 'Monte Calro Simulation' IEEE Journal on Select Vol.6. pp 58-66. 1988
  4. Sklar, B. Digital Communication : Fundamentals and Applications, Prentice Hall, pp.323-428, 1988
  5. T.K. Truong, Ming-Tang Shih and E H Satorius, 'A VLSl Design for a Trace-Back Viterbi Decoder' IEEE Trans Commun., Vol.40, No.30. March 1992
  6. TSUNWHACHI, 'A Scarce-State-Transition Viterbi-Decoder VLSl for Bit Error Correction,' IEEE Journal of Solid State Circuit, Vol.sc-22, No.4. AUG., pp575-581. 1987
  7. 한국전자통신연구원, 155Mbps급 위성 ATM 전송 변복조 핵심기술 개발, 연구보고서, 1997
  8. 한국전자통신연구원, B-WLL용 오류정정 부복호화기 구조설계 및 성능분석, 연구보고서,1999
  9. F. J. MacWilliams, and N. J. Sloane, The Theory of Error-Correction Codes, North Holland, New York, 1997
  10. 정지원 외 4인, '20Mbps급의 64 state Viterbi 복호기 구조 설계 및 CPLD 구현', 한국통신학회 하계 학술 논문집, pp843-846, 1999