전자공학회지 (The Magazine of the IEIE)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

순차회로의 테스트생성 기술

  • 최호용 (충북대학교 전기전자공학부)
  • 발행 : 1998.11.01
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초록

키워드

참고문헌

  1. IBM Journal of Research and Development v.10 no.4 Diagnosis of automata failures: A calculus and a method J. P. Roth
  2. IEEE Trans. on Computers. v.C-30 no.3 An implicit enumeration algorithm to generate tests for combinational logic circuits P. Goel
  3. IEEE Trans. on Computers. v.C-30 no.12 On the acceleration of test generation algorithms H. Fujiwara;T. Shimono
  4. ACM/IEEE Proc. Design Automation Conf. A topological search algorithm for ATPG T. Kirkland;M. R. Mercer
  5. IEEE Trans. on Computer-Aided Design v.CAD-7 no.1 SOCRATES: A highly efficient automatic test pattern generation system M. H. Schulz;E. Trischler;T. M. Sarfert
  6. Proc. Int. Symposium Cicuits and Systems Combinational profiles of sequential benchmark circuits F. Brglez;D. Bryan;K. Kozminski
  7. ACM/IEEE Proc. Design Automation Conf. A logic design structure for LSI testability E. B. Eichelberger;T. W. Williams
  8. Digital Systems Testing and Testable Design M. Abramovici;M. A. Breuer;A. D. Friedman
  9. Proc. (15th) ACM/IEEE Design Automation Conf. EBT: A comprehensive generation technique for highly sequential circuits R. Marlett
  10. Proc. IEEE Int. Test Conf. A sequential circuit test generation system S. Mallela;S. Wu
  11. Proc. (23rd) ACM/IEEE Design Automation Conf. An effective test generation system for sequential circuits R. Marlett
  12. Proc. Int. Conf. Computer Design The BACK algorithm for sequential test generation W.-T. Cheng
  13. IEEE Trans. Computers v.C-20 no.6 A heuristic algorithm for the testing of asynchronous circuits G. R. Putzolu;J. P. Roth
  14. Proc. European Conf. Design Automation HITEC: A test generation package for sequential circuits T. M. Niermann;J. H. Patel
  15. Proc. Int. Conf. Computer-Aided Design A new test generation method for sequential circuits D. H. Lee;S. M. Reddy
  16. Proc. (25th) ACM/IEEE Design Automation Conf. Split circuit model for test generation W. T. Cheng
  17. IRE Trans. Electron. Computers v.11 no.8 The diagnosis of asynchronous sequential switching system S. Seshu;D. N. Freeman
  18. IEEE Trans. Computers v.C-20 no.11 A random and an algorithmic technique for fault detection test generation for sequential circuits M. A. Breuer
  19. IEEE Trans. Computer v.C-24 no.7 The weighted random test-pattern generator H. D. Schnurman;E. Lindbloom;R. G. Carpenter
  20. Proc. Design Automation Conf. CONTEST: A concurrent test generator for sequential circuits V. D. Agrawal;K.-T. Cheng;P. Agrawal
  21. Proc. Int. Conf. Computer-Aided Design CRIS: A test cultivation program for sequential VLSI circuits D. G. Saab;Y. G. Saab;J. A. Abraham
  22. Proc. Design Automation Conf. Sequential circuit test generation in a genetic algorithm framework E. M. Rudnick;J. H. Patel;G. S. Greenstein;T. M. Niermann
  23. Proc. Int. Test Conf. An automatic test pattern generator for large sequential circuits based on genetic algorithms P. Prinetto;M. Rebaudengo;M. Sonza Reorda
  24. Proc. Int. Conf. Computer-Aided Design Iterative[simulation-based genetics+deterministic techniques ]=complete ATPG D. G. Saab;Y. S. Saab;J. A. Abraham
  25. Proc. Design Automation Conf. Combining deterministic and genetic approaches for sequential circuit test generation E. M. Rudnick;J. H. Patel
  26. Proc. European Design and Test Conf. Alternating strategies for sequential circuit ATPG M. S. Hsiao;E. M. Rudnick;J. H. Patel
  27. Genetic Algorithms in Search, Optimization, and Machine Learning D. E. Goldberg
  28. IEEE Trans. Computer-Aided Design v.CAD-7 no.7 Test generation for sequential circuits H-K. T. Ma;S. Devadas;A. R. Newton;A. Sangiovanni-Vincentelli
  29. IEEE Trans. Computer-Aided Design v.CAD-10 no.5 Test generation and verification for highly sequential circuits A. Ghosh;S. Devadas;A. R. Newton
  30. IEEE Trans. Computer-Aided Design v.CAD-12 no.7 Redundancy identification /removal and test generation for sequential circuits using implicite state ennumeration H. Cho;G. D. Hachtel;F. Somenzi
  31. IEICE Trans. v.J76-A no.6 Test generation for sequential circuits based on Boolean function manipulation H. Choi;T. Kohara;N. Ishiura;I. Shirakawa;A. Motohara
  32. IEEE Trans. on Computers v.C-35 no.8 Graph-based algorithms for Boolean function manipulation R. E. Bryant
  33. Proc. (27th) ACM/IEEE Design Automation Conf. Shared binary decision diagram with attributed edges for efficient Boolean function manipulation S. Minato;N. Ishiura;S. Yajima
  34. Proc. IEEE Int. Conf. Implicit state enumeration of finite state machines using BDD's H. J. Touati;H. Savoj;B. Lin;R. K. Brayton;A. Sangiovanni-Vincentelli