Random Pattern Testability of AND/XOR Circuits

Often ESOP(Exclusive Sum of Products) expressions provide more compact representations of logic functions and implemented circuits are known to be highly testable. Motivated by the merits of using XOR(Exclusive-OR) gates in circuit design, ESOP(Exclusive Sum of Products) expressions are considered s the input to the logic synthesis for random pattern testability. The problem of interest in this paper is whether ESOP expressions provide better random testability than corresponding SOP expressions of the given function. Since XOR gates are used to collect product terms of ESOP expression, fault propagation is not affected by any other product terms in the ESOP expression. Therefore the test set for a fault in ESOP expressions becomes larger than that of SOP expressions, thereby providing better random testability. Experimental results show that in many cases, ESOP expressions require much less random patterns compared to SOP expressions.