Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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The Optimization of SONOSFET SPICE Parameters for NVSM Circuit Design

NVSM 회로설계를 위한 SONOSFET SPICE 파라미터의 최적화

  • 김병철 (광운대학교 공대 전자재료공학과) ;
  • 김주연 (광운대학교 공대 전자재료공학과) ;
  • 김선주 (광운대학교 공대 전자재료공학과) ;
  • 서광열 (광운대학교 공대 전자재료공학과)
  • Published : 1998.05.01
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Abstract

In this paper, the extraction and optimization of SPICE parameters on SONOSFET for NVSM circuit design were discussed. SONOSFET devices with different channel widths and lengths were fabricated using conventional 1.2 um n-well CMOS process. And, electric properties for dc parameters and capacitance parameters were measured on wafer. SPICE parameters for the SONOSFET were extracted from the UC Berkeley level 3 model for the MOSFET. And, local optimization of Ids-Vgs curves has carried out in the bias region of subthreshold, linear, saturation respectively. Finally, the extracted SPICE parameters were optimized globally by comparing drain current (Ids), output conductance(gds), transconductance(gm) curves with theoretical curves in whole region of bias conditions. It is shown that the conventional model for the MOSFET can be applied to the SONOSFET modeling except sidewalk effect.

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References

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