전기전자학회논문지 (Journal of IKEEE)

  • 제1권1호
  • /
  • Pages.111-119
  • /
  • 1997
  • /
  • 1226-7244(pISSN)
  • /
  • 2288-243X(eISSN)
한국전기전자학회 (Institute of Korean Electrical and Electronics Engineers)
권호 표지

에지값 결정도(決定圖)에 의한 다치논리함수구성(多値論理函數構成)에 관한 연구(硏究)

A Study on the Construction of Multiple-Valued Logic Functions by Edge-Valued Decision Diagram

  • 한성일 (인하대학교 전자공학과) ;
  • 최재석 (인하대학교 전자공학과) ;
  • 박춘명 (충주산업대학교 컴퓨터공학과) ;
  • 김흥수 (인하대학교 전자공학과)
  • 발행 : 1997.12.01
PDF 다운로드
⟨ 이전 논문 다음 논문 ⟩

초록

본 논문에서는 최근의 디지탈논리시스템의 함수구성시에 도입되고 있는 그래프이론에 바탕을 둔 결정도로부터 새로운 형태의 데이터구조 형태인 에지값 결정도를 추출하는 알고리즘의 한가지 방법을 제안하였다. 그리고 이를 기초로 임의의 m치 n변수의 축약된 함수구성을 도출하는 방법에 대해 논의하였다. 제안한 다치논리함수구성방법은 도식적이며 규칙적이고 정규성을 내포하고 있다.

This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently used in constructing the digital logic systems based on the graph theory. And we discussed the function minimization method of the n-variables multiple-valued functions. The proposed method has the visible, schematical and regular properties.

키워드

참고문헌

  1. ISMVL 90 Toward the Age of the Beyond-Binary Electronics and System Kameyama, M.
  2. Special issue on Multiple-Valued intergrated circuits IEICE TRANS. ELECTRON. v.E76-C no.3 Prospects for multiple-valued intergrated circuits Smith, K.C.;Gulak, P.G.
  3. IEEE Trans. Comput. v.C-33 Multiple-Valued logic - its status and its future Hurst, S.L.
  4. IEICE Trans. Electron. v.E76-C no.3 Prospects of Multiple-Valued VLSI Processors Hanyu, T.;Kameyama, M.;Higuchi, T.
  5. Computer Science and Multiple-Valued Logic Theory and Applications Rine, David C.
  6. Multiple-Valued Logic: an Introduction Epstein, G.
  7. ISMVL 92 On the Performance of Multivalued intergrated Circuits: Past. Present and Future Etiemble, D.
  8. Graph Theory Gould, R.
  9. GRAPH an Introductory Approach Wilson, R.J.;Watkins, J.J.
  10. IEEE Trans. Comput. v.C-27 no.6 Binary Decision Diagrams Aker, S.B.
  11. IEEE Trans. Comput. v.C-35 no.8 Graph-Based Algorithms for Boolean Function manipulations Bryant, R.E.
  12. IEEE Proc. of Symposium on Multiple-Valued Logic Multiple-Valued Logic Design Tools Miller, D.M.
  13. IEEE Trans. Comput. v.43 no.10 Efficient Boolean Manipulation with OBDD's can be Extended to FBDD's Gergoy, J.;Meinel, C.
  14. ISMVL 95 Planar Multiple-Valued Decision Diagrams Sasao, T.;Butler, J.T.
  15. 電子工學會論文誌 v.32 no.6 決定다이아그램에 의한 多値組合論理시스템 構成에 관한 硏究 朴春明;金興壽
  16. IEEE 26th proceedings on ISMVL A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams Sasao, T.;Butler, Jon T.
  17. 29th ACM/IEEE Desigh Automation Conference Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification Lai, Yung-Te;Sastry, Sarma
  18. IEEE Trans. on Computers v.45 no.2 Formal Verification Using Edge-Valued Binary Decision Diagrams Lai, Yung-Te;Pedram, M.;Vrudhula, S.B.K.
  19. Modem Logic Design Green, D.
  20. Discrete and Switching Functions Davio, M.;Deschamps, Jean-Pierre;Thayse, Andre
  21. Finite Fields for Computer Science and Engineers McEliece, R.J.