고속 메모리 동작을 위한 내부 클럭 발생 회로의 기술동향

New DRAM Technologies : A Comprehensive Analysis of the New Architectures(Second Edition) Steven A. Przybylski
IEEE J. Solid-State Circuits v.29 250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture Y. Takai(et al.)
IEEE J. Solid-State Circuits v.29 16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate Y. H. Choi(et al.)
Symp. VLSI circuits Capacitance coupled Bus with Negative Delay Circuit for High speed and Low Power (10GB/s<500mW) Synchronous DRAMs T. Yamada(et al.)
IEEE J. Solid-State Circuits v.31 A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay T. Sakei(et al.)
Symp. VLSI circuits Skew Minimization Techniques for 256M-bit Synchronous DRAM and beyond J. M. Han(et al.)
IEEE International Solid-State Circuits Conf. A 256Mb SDRAM Using a Register-Controlled Digital DLL A. Hatakeyama(et al.)