Memory Test의 문제와 전망

참고문헌

1. ACM Computing Survey v.15 no.3 Functional testing of semiconductor random access memories M.S.Abadir;H.K.Reghbati
2. IEEE Tr. Comput. v.38 no.4 Diagnosis and repair of memory with coupling faults M.F.Chang;W.K.Fuchs;J.H.Patel
3. IEEE J. Solid State Circuits v.24 no.5 A 60-ns 16Mbit DRAM with a minimized sensing deley caused by bit line stray capacitance S.Chou(et al.)
4. Chip Size Packaging Developments, TechSearch International R. T. Crowley;T. W. Goodman;E. J. Vardaman
5. IEEE Tr. Comput. v.39 no.2 Fault diagnosis of RAM's from random testing experiments R. David;A. Fuentes
6. IEEE Test Conf. A realistic self-test machine for static random access memories R. Dekker;F. Beenker;L.Thijssen
7. IEEE J. Solid State Circuits v.25 no.2 A built-in self-test algorithm for row/column pattern sensitive faults in RAM M. Franklin;K. K. Saluja;K. Kinoshita
8. IEEE J. Solid State Circuits v.24 no.1 A built-in Hamming code ECC circuit for DRAM's K. Furutani(et al.)
9. IEEE J. Solid-State Circuits v.25 no.1 A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs T. Furuyama(et al.)
10. IEEE Tr. Comput. v.C"24 no.2 Detection of pattern sensitive faults in random access memories J. P. Hayes
11. IEEE Int'l Workshop on Memory Technology, Design and Testing A built-in self-test scheme for 256Meg SDRAM F. Hii;T. Powel;D. Cline
12. IEEE 29th Proc. of Relaibility Physics Symposium A new failure mechanism related to grain growth in DRAMs T. Katayama(et al.)
13. Digest of Papers IEEE Int'l Solid State Circuits Conf. Optimized redundancy selection based on a failure related yield model for 64Mb DRAM and beyond S. Kikuda(et al.)
14. ISSCC Digest of Tech. Papers A 30ns 64Mb DRAM with built-in self-test and repair function H. Koike(et al.)
15. IEEE Proceedings v.83 no.4 Trends in low power RAM circuit technologies K. Itoh
16. IEEE J. Solid State Circuits v.SC-12 no.6 An integrated test concept for switched capacitor dynamic MOS RAM's T. C. Lo;M. R. Guidry
17. IEEE Test Conf. A new architecture for parallel testing in VLSI memories Y. Matsuda(et al.)
18. Int'l Test Conf., Proc. A novel built-in self-refair approach to VLSI memory yield enhancement P. Mazumder;J. S. Yih
19. IEEE J. Solid-State Circuits v.25 no.1 A multibit test trigger circuit for megabit SRAM's F. Miyaji(et al.)
20. IEEE 29th Proc. of Reliability Physics Symposium Threshold voltage instability and charge retention in nonvolatile memory cell with nitride/oxide S. Mori(et al.)
21. IEEE Tr. Compt. v.40 no.10 Testing for coupled cells in random-access memories J. Savir;W. H. McAnney;S. R. Vecchio
22. IEEE J. Solid State Circuits v.25 no.4 A 55ns 16Mb DRAM with built-in self test function using microprogram ROM T. Takeshima(et al.)
23. Asian Electronics Engineers v.4 no.6 New generation test systems meet VRAM testing challenge A. Tejeda;G. Corner
24. Testing Semiconductor memories ; Theory of Practice A. J. van de Goor
25. IEEE J. Solid State Circuits v.26 no.1 Variable bit organzation as a new test function for standard memories T. Wada(et al.)
26. IEEE J. Solid-State Circuits v.26 no.3 Crosstalk and transient analyses of high-speed interconnects and packages H. You;M. Soma
27. IEEE Tr. CAD v.19 no.12 Implementation of VLSI self-testing by regularization Y. You;J. P. Hayes
28. Int'l Conf. on Elect., Info. and Comm. Testing of memories with tolerable defects Y. You
29. SEMICON/KOREA '91, Technical Symposium Multi-mega bit memory test technology Y. You
30. 공학기술 v.3 no.3/4 고속 DRAM 신기술 SyncLink 동향 안승환