The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
권호 표지

ASIC design of high speed CAM for connectionless server of ATM network

ATM망의 비연결형 서버를 위한 고속 CAM ASIC 설계

  • 백덕수 (국립이리농공전문대 전자과) ;
  • 김형균 (원광대학교 전자공학과) ;
  • 이완범 (원광대학교 전자공학과)
  • Published : 1997.07.01
Download PDF
⟨ Previous Next ⟩

Abstract

Because streaming mode connection server suitable to wide area ATM networks performs transmission, reception and lookup with time restriction for the transmission time of a cell, it has demerits of large cell loss incase that burst traffic occurs. Therefore, in this paper to decrease cell loss we propose a high speed CAM (Content Addressable Memory) which is capable of processing data of streaming mode connections server at a high speed. the proposed CAM is applied to forwarding table VPC map which performs function to output connection numbers about input VPI(Virtual Path Identifier)/VCI(Virtual Channel Identifier). The designed high speed CAM consist of DBL(Dual Bit Line) CAM structure performed independently write operation and match operation and two-port SRAM structure. Also, its simulation verification and full-custom layout is performed by Hspice and Composs tools in 0.8 .$\mu$m design rule.

Keywords

References

  1. Proceeding of INFOCOM 92 LAN/MAN Interconnection to ATM:A Simulation Study M. Gerla;T.-Y. Tai;G. Gallassi
  2. ICC Performance Comparison of Badwidth Allocation Mechmisms for LAN/MAN Interworking though an ATM Network Kiyoshi Shimokoshi
  3. ITU-T Recommendation 1.327:B-ISDN Functional Architecture
  4. IEEE Communication Magazine Connectionless Service for Public ATM Networks Brett J. Vickers;Tatsuya Suda
  5. Technical Report #94-41, Dept. of Information and Computer Science, UC lrvine The Internetworking of Connectionless Data Networks over Public ATM:Connectionless Server Design and Performance Duke P. Hong;Brett J. Vickers;Tatsuya Suda;Carlos Oliveira
  6. ISSCC Dig. Tech. Papers. a 1.2-M transistor, 33MHz, 20-bit dictionary search process ULSI for a machine translation system M. Motomura (et al.)
  7. IEEE J. of Solid-state circuit v.sc-5 no.5 Intergrated Circuit Content Addressable Memories James T. Koo
  8. IEEE J. of solid-state circuit v.24 no.23 A Content Addressable Memory Management Unit with On-Chip Data Cache A. K. Goksel (et al.)
  9. IEEE J. of solid-state circuits v.23 no.2 A 9-kbit Associative Memory for High-speed Parallel Processing Applications Simon R. Jones
  10. Proceeding of the 14th Conference on Solid State Devices v.22 A IK bits Associative Memory LSI Tactanobu Nikaido
  11. IEEE J. Solid-State Circuits v.25 no.5 A 23ns 4Mb CMOS SRAM with 0.2μA Standby Current K. Sasaki;K. Ishibashi (et al.)
  12. IEEE J. Solid-State Circuits v.23 no.5 A 25ns Low-Power Full-CMOSIMbit(128×8) SRAM Sow T. C (et al.)