Journal of Electrical Engineering and information Science

The Korean Institute of Electrical Engineers (대한전기학회)
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Effects of Offset Gate on Programing Characteristics of Triple Polysilicon Flash EEPROM Cell

  • Kim, Nam-Soo (Dept. of Electrical nd Electronics Engineering, Chungbuk National University) ;
  • Choe, Yeon-Wook (Dept. of Control and Instrumentation Bukyong National University) ;
  • Kim, Yeong-Seuk (Dept. of Electrical nd Electronics Engineering, Chungbuk National University)
  • Published : 1997.06.01
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Abstract

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

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References

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