Analysis on the breakdown characteristics of ESD-protection NMOS transistors based on device simulations

소자 시뮬레이션을 이용한 ESD 보호용 NMOS 트랜지스터의 항복특성 분석

Utilizing 2-dimensional device simulations incorporating lattic eheating models, we analyzed in detail the DC breakdown characterisics of NMOS trasistors with different structures, which are commonly used as ESD protection transistors. The mechanism leading to device failure resulting from electrostatic discharge was explained by analyzing the 1st and 2nd breakdown characteristics of LDD devices. Also a criteria for more robust designs of NMOS transistor structures against ESD was suggested by examining the characteristics changes with changes in structural parameters such as the LDD doping concentration, the drain junction depth, the distance between source/drain contacts, and the source junction area.