전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제33A권10호
- /
- Pages.123-129
- /
- 1996
- /
- 1016-135X(pISSN)
NMOSFET에서 LDD 영역의 전자 이동도 해석
Analysis of electron mobility in LDD region of NMOSFET
초록
LDD structure is widely accepted in fabricating short channel MOSFETs due to reduced short channel effect originated form lower drain edge electric field. However, modeling of the LDD device is troublesome because the analysis methods of LDD region known are either too complicated or inaccurate. To solve the problem, this paper presents a nonlinear resistance model for the LDD region based on teh fact that the electron mobility changes with positive gate bias because accumulation layer of electrons is formed at the surface of the LDD region. To prove the usefulness of the model, single source/drain and LDD nMOSFETs were fabricated with 0.35
키워드