전자공학회논문지A (Journal of the Korean Institute of Telematics and Electronics A)
- 제33A권10호
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- Pages.115-122
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- 1996
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- 1016-135X(pISSN)
루프인식 속도를 개선한 300MHz PLL의 설계 및 제작
A 300MHz CMOS phase-locked loop with improved pull-in process
초록
A 300MHz PLL including FVC (frequency to voltage converter) is designed and fabricated in 0.8
키워드