A FPGA implementation of a full-digital code acquisition/Tracking Loop for the CDMA direct-sequence spread-spectrum signals

대역 제한된 직접 시퀀스 CDMA 확산 대역 신호를 위한 전 디지탈 부호 획득 및 추적 루우프 FPGA 구현

A noncoherent full-digital PN(pseudo noise) code acquisition/tracking loop has been presetned and implemented in FPGA for the CDMA band-limited direct-sequence spread-spectrum (DS-SS) signals. It employs a simple decimator to control of local PN code phase to lower the hardware cost, and a second order loop to enable the more accurate tracking. The proposed acquisition/tracking loop has been designed in RTL-level VHDL, synthesized into logic gates using the design analyzer of synopsys software, implemented in an ALTERA FPGA chip, and tested. The number of logic gates used in the implemented FPGA chip is around 7000. The functionality has been verified using a PC interface circuitry and a logic analyzer.