Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 32A Issue 1
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- Pages.138-145
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- 1995
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- 1016-135X(pISSN)
Design of HALL effect integrated circuit with reduced wolgate offset in silicon bipolar technology
옵셋전압을 저감시킨 실리콘 바이폴라 홀 IC 설계
Abstract
The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90
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