Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 32A Issue 12
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- Pages.220-228
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- 1995
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- 1016-135X(pISSN)
An Architecture Design of a Multi-Stage 12-bit High-Speed Pipelined A/D Converter
다단 12-비트 고속 파이프라인 A/D 변환기의 구조 설계
Abstract
An optimized 4-stage 12-bit pipelined CMOS analog-to-digital converter (ADC) architecture is proposed to obtain high linearity and high yield. The ADC based on a multiplying digital-to-analog converter (MDAC) selectively employs a binary-weighted-capacitor (BWC) array in the front-end stage and a unit-capacitor (UC) array in the back-end stages to improve integral nonlinearity (INL) and differential nonlinearity (DNL) simultaneously whil maintaining high yield. A digital-domain nonlinear error calibration technique is applied in the first stage of the ADC to improve its accuracy to 12-bit level. The largest DNL error in the mid-point code of the ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is reduced by avoiding a code-error symmetry observed in a conventional digitally calibrated ADC is simulated to prove the effectiveness of the proposed ADC architecture.
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