Enhancement of Clock Advancement in Parallel Logic Simulation

병렬처리 논리 시뮬레이션에서 클럭 진행의 개선

Efficient event evaluation and propagation techniques are proposed to enhance the advancement of simulation clocks of conservative and optimistic logic simulation protocols on parallel processing environments. The first idea of the techniques proposed in this paper is to allow more than one event evaluation per simulation cycle and to pack more than one propagation event in a single message. The second idea is to use advancement windows resulted in good performance in parallelism and execution times.