Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 30A Issue 3
- /
- Pages.114-129
- /
- 1993
- /
- 1016-135X(pISSN)
FFT Array Processor System with Easily Adjustable Computation speed and Hardware Complexity
계산속도와 하드웨어 양이 조절 용이한 FFT Array Processor 시스템
Abstract
A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.
Keywords