Journal of the Korean Institute of Telematics and Electronics A (전자공학회논문지A)
- Volume 29A Issue 2
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- Pages.33-40
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- 1992
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- 1016-135X(pISSN)
The Design of Variable Delay Line Circuit Using Indirect Frequency Synthesizer
간접 주파수 합성기를 이용한 가변 신호지연 회로 설계
Abstract
The design method of signal delay line system using indirect frequency synthesizer is presented. The variable signal delay line system with 2[nsec] step of delay time at center frequency 60[MHz], bandwidth 500[KHz] and range 5.24-5.81[x10S0-6Tsec] is designed and fabricated. The results were met with good characteristics to be variable delay time of average 2.01[nsec] per step.
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