The Transactions of the Korean Institute of Electrical Engineers (대한전기학회논문지)

The Korean Institute of Electrical Engineers (대한전기학회)
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An Advanced Model of on-Resistance for Low Voltage VDMOS Devices

저전압 VDMOS의 ON-저항 모델

  • 김일중 (서울대 대학원 전기공학과) ;
  • 김성동 (서울대 대학원 전기공학과) ;
  • 최연익 (아주대 공대 전자공학과) ;
  • 한민구 (서울대 공대 전기공학과)
  • Published : 1992.03.01
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Abstract

An advanced on-resistance model of VDMOS devices in the low voltage regimes is proposed and verified by 2-D device simulations. The model considers the lateral gaussian doping profiles in the channel region and exact current spreading angles in the epitaxial layer for both linear and cellular geometries by employing the conformal mapping, It is found out that the on-resistance of low voltage VDMOS may be overestimated considerably if it is analyzed by the conventional method. The 2-D device simulation results show that the proposed model is valid for the VDMOS devices in the low voltage regimes.

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