References
- IEEE Trans.Electrom Device v.ED-29 Effect of Scaling of Interconnections on the Time Delay of VLSI Circuits K.C. Saraswat;Mohamad
- IEEE Trans. Electron Devices v.ED-26 The Evolution of Digital Electronics Toward VLSI R.W. Keyes
- Semiconductor International Pieter Burggraaf
- Personal Communications S.H. Hong
- J. Appl. Phys. v.58 no.2 Secondary Grain Growth in Thin Films of Semiconductors : Theoretical Aspects C.V. Thomson
- J. Appl. Phys. v.0 no.1 Analysis of the Effects of Annealing on Resistivity of Chemical Vapor Deposition Tungsten Silicide Films Yoshimi Shioya
- J. Appl. Phys. v.52 no.8 Properties of Tungsten Silicide Film on Polycrystalline Silicon M.Y. Tasi;F.M. d'Heurle;C.S. Petersson;R.W. Johnson
- J. Appl. Phys. v.62 no.7 Annealing and Oxidation Behavior of Low-Pressure CVD Tungsten Silicide Layers on Poly-Si Gate D.K. Sadana;A.E. Morgan;M.H. Norcott;S. Naik
- J. Electrochem. Soc. v.129 no.10 Thermal Oxidation of Heavily Phosphorus Doped Thin Films of Poly crystalline Silicon K.C. Saraswat;H. Singh
- J. Appl. Phys. v.54 Interface Effects in the Formation of Silicon Oxide on Metal Silicide Layers over Silicon Substrates J.E. Baglin;F.M. d'Heurle;C.S. Petersson